• Journal of the Institute of Convergence Signal Processing
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• v.4 no.2
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• pp.61-69
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• 2003

In this paper, we developed the U parameter test system which inspects the property of DC parameter for semiconductor products. The developed system is interfaced by IBM-PC. It is consisted of CPLD part, ADC (Analogue to Digital Converter), DAC (Digital to Analogue Converter), voltage/current source, variable resistor and measurement part. In the proposed system, we have designed the constant voltage source and the constant current source in a part. The CPLD part is designed by VHBL, which it generates the control and converts the serial data to parallel data. The proposed system has two test channels and it operates VFCS mode and CFVS mode. The range of test voltage is from 0[V] to 100[V], and the range of test current is from 0[mA] to 100[mA)]. The diode is tested. The test results have a good performance.

• Proceedings of the KIPE Conference
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• 2010.11a
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• pp.173-174
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• 2010

In this paper, authors propose a new buck-boost converter of discontinuous conduction mode (DCM) added electric isolation. The proposed converter with DCM eliminates the complicated circuit control requirement and reduces the size of components. The general converters of high efficiency are made that the power loss of the used switching devices is minimized. To achieve the soft switching operation of the used control switches, the proposed converter uses a lossless snubber capacitor. The proposed converter achieves the soft-switching for all switching devices without increasing their voltage and current stresses. The result is that the switching loss is very low and the efficiency of converter is high. The soft switching operation of the proposed converter is verified by digital simulation and experimental results.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.6
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• pp.1154-1162
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• 2016

This paper proposes a fast-transient digital LDO(Low dropout) regulator with binary-weighted current control technique. Conventional digital LDO takes a long time to stabilize the output voltage, because it controls the amount of current step by step, thus ringing problem is generated. Binary-weighted current control technique rapidly stabilizes output voltage by removing the ringing problem. When output voltage reliably reaches the target voltage, It added the FRZ mode(Freeze) to stop the operation of digital LDO. The proposed fast response digital LDO is used with a slow response DC-DC converter in the system which rapidly changes output voltage. The proposed digital controller circuit area was reduced by 56% compared to conventional bidirectional shift register, and the ripple voltage was reduced by 87%. A chip was implemented with a $0.18{\mu}F$ CMOS process. The settling time is $3.1{\mu}F$ and the voltage ripple is 6.2mV when $1{\mu}F$ output capacitor is used.

• The Transactions of the Korean Institute of Power Electronics
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• v.19 no.6
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• pp.488-493
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• 2014

This paper presents a carrier-based pulse-width modulation(PWM) method for reducing the common-mode voltage of a three-level four-leg converter. The idea of the proposed PWM method is intuitive and easy to be implemented in digital signal processor-based converter control systems. On the basis of the analysis of space-vector PWM(SVPWM) and sinusoidal PWM(SPWM) switching patterns, the fourth leg pole voltage of the three-phase converter called "f leg pole voltage" is manipulated to reduce the common-mode voltage. To synthesize f leg pole voltage for the suppression of the common-mode voltage, positive and negative pole voltage references of f leg are calculated. An offset voltage is also deduced to prevent the distortion of a, b, and c phase voltages. The feasibility of the proposed PWM method is verified by simulation and experimental results. The common-mode voltage of the proposed PWM method in peak-to-peak value is 33% in comparison with that of the conventional SVPWM method. The transition number of the common-mode voltage is also reduced to 25%.

• Proceedings of the KIPE Conference
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• 2007.07a
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• pp.29-31
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• 2007

This is experimental result which is reported with use the dsPIC30F2020 16-Bit SMPS microprocessor of MicroChip company which composes a digital control circuit and it applies in switched-mode power supply unit. The basic topology consist of the synchronous rectifier in a two transistor forward converter. In a experiment, it is used from microprocessor to do with A/D conversion and it is embodied with PID controls in order to detect a over-current, over-voltage, over-temperature and output voltage.

• Proceedings of the KWS Conference
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• 2002.05a
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• pp.65-67
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• 2002

The gas metal arc welding(GMAW) is regarded as one of the best candidate for welding automation in industrial joining application. It is important to monitor the weld quality for the high performance of weld automation. The measured analog signal is frequency analyzed by digital signal process method. In order to observe the welding phenomena and control welding condition, arc light, voltage, and current are measured at the same time. They are analyzed and compared with arc sound. for these experiments, a power source of constant voltage characteristics was used in the pure metal transfer mode.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.10
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• pp.40-47
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• 2016

In this paper, a dual mode buck converter with an ability to change mode is proposed, which is suitable particularly for portable device. The problem of conventional mode control circuit is affected by load variation condition such as suddenly or slowly. To resolve this problem, the mode control was designed with slow clock method. Also, when change from the PFM(Pulse Frequency Modulation) mode to the PWM(Pulse Width Modulation) mode, to use the counter to detect a high load. And the user can select mode transition point in load range from 20mA to 90mA by 3 bit digital signal. The circuits are implemented by using BCDMOS 0.18um 2-polt 3-metal process. Measurement environment are input voltage 3.7V, output voltage 1.2V and load current range from 10uA to 500mA. And measurement result show that the peak efficiency is 86% and ripple voltage is less 32mV.

• Journal of the Korean Society of Radiology
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• v.14 no.5
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• pp.635-642
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• 2020

The purpose of this study was to analysis the effects of shielding area of field configuration with changing of sensitivity and density on tube current (milliampere-seconds, mAs) and image quality in automatic exposure control (AEC) system. The equipment used a digital radiography device (Digital Diagnost, Philips, Netherlands), which has a integral type with an X-ray tube and an indirect digital detector. The AEC system conditions were consisted of 9 setting environments, that mode changing of the sensitivity (S200, S400, S800) and the density (+2.5, 0, -2.5). The tube current evaluated automatically exposed mAs under 81 combination conditions crossed by AEC conditions in fixed at 40 kVp. The image quality evaluated the radiographic images that selected valid images by visual assessment the radiographic images of the self-produced conical pyramid phantom and then measured their signal to noise ratio (SNR). As a result, the maximum tube current was 60.0 mAs that automatically exposed conditions were the 100% of shielding area and the sensitivity of S200 and the density of +2.5. The minimum tube current was 0.9 mAs with non-shielding area and the sensitivity of S800 and the density of -2.5. When the shielded area 0% with the sensitivity of S200 and the density of +2.5, the maximum SNR was the highest as 25.2. But when the shielded area 25% with the sensitivity of S800 and the density of -2.5, the minimum SNR was the lowest as 4.7.

• Proceedings of the KIEE Conference
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• 1991.07a
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• pp.552-554
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• 1991

In this paper is applied Sliding Mode method to position control system with Permanent Magnetic Synchronous Motor (PMSM), with realized a Digital Controller with Micro-Processor. And also, this paper proposes an Algorithm to compen-sate chattering of torque current to added controled parameter to continuous function of torque current.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.42 no.11
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• pp.61-66
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• 2005

This paper describes a 10-bit 210MHz CMOS current-mode Digital-to-Analog Converter (DAC) consisting of 6 bit MSB current cell matrix Sub-DAC, 2 bit mSB unary current source Sub-DAC, and 2 bit LSB binary weighting Sub-DAC for Wireless LAN application. A new deglitch circuit is proposed to control a crossing point of signals and minimize a glitch energy. The proposed 10-bit CMOS current mode DAC was designed by a $0.35{\mu}m$ CMOS double-poly four-metal technology rate of 210MHz, DNL/INL of ${\pm}0.7LSB/{\pm}1.1LSB$, a glitch energy of $76pV{\cdot}sec$, a SNR of 50dB, a SFDR of 53dB at 200MHz sampling clock and power dissipation of 83mW at 3.3V