• Journal of the Korean Society of Surveying, Geodesy, Photogrammetry and Cartography
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• v.27 no.6
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• pp.741-747
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• 2009

For construction of 3D virtual city models, airborne digital cameras, laser scanners, multi-oblique photograph systems and other devices are currently being used. With such advanced techniques, precise 3D spatial information can be collected and high quality 3D city models can be built in a considerably large area. The 3D spatial information to be built has to provide the latest information that quickly reflects the causes of any change due to urban development. In this study, a UAV photogrammetric method using low cost UAV and digital camera was proposed to acquire and update 3D spatial information effectively on small areas where information continuously change. In the proposed UAV photogrammetric method, the elements of interior orientation were acquired through camera calibration and the vertical and oblique photographs were taken at 9 points and the 3D drawing of ground control points and buildings was performed using 20 images among the pictured images. This study also analyzed the accuracy of the proposed method comparing with ground survey data and digital map in order to examine whether the method can be used in on-demand 3D spatial information update on relatively small areas.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.7
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• pp.87-95
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• 2013

In this paper, 2.5 Gb/s burst-mode clock and data recovery(CDR) is presented. Digital frequency calibration scheme is adopted to eliminate mismatch between the input data rate and the output frequency of the gated voltage controlled oscillator(GVCO) in the clock recovery circuitry. A jitter rejection scheme is also used to reduce jitter caused by input data. The proposed burst-mode CDR is designed using 0.11 ${\mu}m$ CMOS technology. Post-layout simulations show that peak-to-peak jitter of the recovered data is 14 ps with 0.1 UI input referred jitter, and maximum tolerance of consecutive identical digit(CID) is 2976 bits without input data jitter. The active area occupies 0.125 $mm^2$ without loop filter and the total power consumption is 94.5 mW.

• Journal of the Korean Society of Surveying, Geodesy, Photogrammetry and Cartography
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• v.28 no.1
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• pp.161-168
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• 2010

This study aims to propose a method that shall rapidly acquire 3D information of the fast and frequently changing city areas by using the images taken by the UAV photogrammetric method, and to develop the process of the acquired data. For this study's proposed UAV photogrammetric method, low-cost UAV and non-metric digital camera were used. The elements of interior orientation were acquired through camera calibration. The artificial 3D model of the artificial structures was constructed using the image data photographed at the target area and the results of the ground control point survey. The digital surface model was created for areas that were changed due to a number of civil works. This study also analyzes the proposed method's application possibility by comparing a 1/1,000 scale digital map and the results of the ground control point survey. Through the above studies, the possibilities of constructing a 3D virtual city model renewal of 3D GIS database, abstraction of changed information in geographic features and on-demand updating of the digital map were suggested.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.2
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• pp.414-422
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• 2013

This paper describes a 10-bit 10-MS/s asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) using a split-capacitor-based differential digital-to-analog converter (DAC). SAR logic and comparator are asynchronously operated to increase the sampling frequency. The time-domain comparator with an offset calibration technique is used to achieve a high resolution. The proposed 10-bit 10-MS/s asynchronous SAR ADC with the area of $140{\times}420{\mu}m^2$ is fabricated using a 0.18-${\mu}m$ CMOS process. Its power consumption is 1.19 mW at 1.8 V supply. The measured SNDR is 49.95 dB for the analog input frequency of 101 kHz. The DNL and INL are +0.57/-0.67 and +1.73/-1.58, respectively.

• The Proceedings of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.11 no.1
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• pp.114-122
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• 1997

This paper describes the design and development of a smart digital load cell used forweighing installations. Sice the load cell sensor to be used is very sensitive for weight cariation, the load cell must have the temperature stability, low-drift and the high-resolution of the A/D conversion for accuracy. A new analog circuit which is controlled by one chip micro-processer has been developed to reduce the offset voltage and the drift characteristics of operational amplifiers, and has been adapted into the digital load cell. Also, a software algorithm has been developed to obtain the stable and accurate A/D conversion. This software includes a RS-485 communication program to control the digital load cell, which gives a capability of backing-up the calibration data and transferring control data. The simulation and evaluation of the designed digital load cell has been shown as having the good performance. which will give useful application to the weighing installations as a remote weighing sensor.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.18 no.3
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• pp.562-568
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• 2014

With the development of computer technology, augmented reality (Augmented Reality, AR) technology in the future, one of the main directions of development of human interface technology is emerging. On augmented reality based on the design and implementation of a digital business card system. In this paper, a Smartphone is simply information through recognizable digital business card contains information about the system. Digital business card system is compared to the way existing hardware in a way visually-based high precision. In addition, registered as a 3D computer vision of augmented reality technology skills and real-world situations convergence technology for research. Future research, 3D electronic map for Smartphone apps as of the application user interface on the side for research is needed.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.12 s.354
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• pp.55-64
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• 2006

This work proposes a calibration-free 14b 70MS/s 0.13um CMOS ADC for high-performance integrated systems such as WLAN and high-definition video systems simultaneously requiring high resolution, low power, and small size at high speed. The proposed ADC employs signal insensitive 3-D fully symmetric layout techniques in two MDACs for high matching accuracy without any calibration. A three-stage pipeline architecture minimizes power consumption and chip area at the target resolution and sampling rate. The input SHA with a controlled trans-conductance ratio of two amplifier stages simultaneously achieves high gain and high phase margin with gate-bootstrapped sampling switches for 14b input accuracy at the Nyquist frequency. A back-end sub-ranging flash ADC with open-loop offset cancellation and interpolation achieves 6b accuracy at 70MS/s. Low-noise current and voltage references are employed on chip with optional off-chip reference voltages. The prototype ADC implemented in a 0.13um CMOS is based on a 0.35um minimum channel length for 2.5V applications. The measured DNL and INL are within 0.65LSB and l.80LSB, respectively. The prototype ADC shows maximum SNDR and SFDR of 66dB and 81dB and a power consumption of 235mW at 70MS/s. The active die area is $3.3mm^2$.

• Korean Journal of Remote Sensing
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• v.30 no.1
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• pp.149-160
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• 2014

Recently studies on application development and utilization using sensors and devices embedded in smartphones have flourished at home and abroad. This study aimed to analyze the accuracy of the images of smartphone to determine three-dimension position of close objects prior to the development of photogrammetric system applying smartphone and evaluate the feasibility to use. First of all, camera calibration was conducted on autofocus and infinite focus. Regarding camera calibration distortion model with balance system and unbalance system was used for the decision of lens distortion coefficient, the results of calibration on 16 types of projects showed that all cases were in RMS error by less than 1 mm from bundle adjustment. Also in terms of autofocus and infinite focus on S and S2 model, the pattern of distorted curve was almost the same, so it could be judged that change in distortion pattern according to focus mode is very little. The result comparison according to autofocus and infinite focus and the result comparison according to a software used for multi-image processing showed that all cases were in standard deviation less than ${\pm}3$ mm. It is judged that there is little result difference between focus mode and determination of three-dimension position by distortion model. Lastly the checkpoint performance by total station was fixed as most probable value and the checkpoint performance determined by each project was fixed as observed value to calculate statistics on residual of individual methods. The result showed that all projects had relatively large errors in the direction of Y, the direction of object distance compared to the direction of X and Z. Like above, in terms of accuracy for determination of three-dimension position for a close object, the feasibility to use smartphone camera would be enough.

• Journal of The Korean Society of Agricultural Engineers
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• v.59 no.3
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• pp.83-96
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• 2017

This study presented a surface water quality modeling framework considering the spatial resolution of pollutant load estimation to better represent stream water quality characteristics in the Saemangeum watershed which has been focused on keeping its water resources sustainable after the Saemangeum embankment construction. The watershed delineated into 804 sub-watersheds in total based on the administrative districts, which were units for pollutant load estimation and counted as 739 in the watershed, Digital Elevation Model (DEM), and agricultural structures such as drainage canal. The established model consists of 7 Mangyung (MG) sub-models, 7 Dongjin (DJ) sub-models, and 3 Reclaimed sub-models, and the sub-models were simulated in a sequence of upstream to downstream based on its connectivity. The hydrologic calibration and validation of the model were conducted from 14 flow stations for the period of 2009 and 2013 using an automatic calibration scheme. The model performance to the hydrologic stations for calibration and validation showed that the Nash-Sutcliffe coefficient (NSE) ranged from 0.66 to 0.97, PBIAS were -31.0~16.5 %, and $R^2$ were from 0.75 to 0.98, respectively in a monthly time step and therefore, the model showed its hydrological applicability to the watershed. The water quality calibration and validation were conducted based on the 29 stations with the water quality constituents of DO, BOD, TN, and TP during the same period with the flow. The water quality model were manually calibrated, and generally showed an applicability by resulting reasonable variability and seasonality, although some exceptional simulation results were identified in some upstream stations under low-flow conditions. The spatial subdivision in the model framework were compared with previous studies to assess the consideration of administrative boundaries for watershed delineation, and this study outperformed in flow, but showed a similar level of model performance in water quality. The framework presented here can be applicable in a regional scale watershed as well as in a need of fine-resolution simulation.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2012.05a
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• pp.88-90
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• 2012

This paper describes a 10-bit 10-MS/s asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) with a rail-to-rail input range. The proposed SAR ADC consists of a capacitor digital-analog converter (DAC), a SAR logic and a comparator. To reduce the frequency of an external clock, the internal clock which is asynchronously generated by the SAR logic and the comparator is used. The time-domain comparator with a offset calibration technique is used to achieve a high resolution. To reduce the power consumption and area, a split capacitor-based differential DAC is used. The designed asynchronous SAR ADC is fabricated by using a 0.18 um CMOS process, and the active area is $420{\times}140{\mu}m^2$. It consumes the power of 0.818 mW with a 1.8 V supply and the FoM is 91.8 fJ/conversion-step.