• Journal of the Korean Institute of Landscape Architecture
• /
• v.36 no.3
• /
• pp.63-74
• /
• 2008

With the awareness that Sinyeongwol Sipgyeong(ten scenic spots in Yeongwol) were designed too hastily and only for PR purposes after the change in the tourism environment, this paper indicates that most tourism and culture sources in Yeongwol are related to King Danjong, the sixth king of the Joseon Dynasty. This study proposes a 'Storytelling Plan' for the landscape content called 'Cultural Landscapes - Yeongwol Palgyeong(eight scenic spots in Yeongwol)' after reviewing types and content of Yeongwol Palgyeong through the halo effect of the well-known sad history of King Danjong and the cultural value of Yeongwol. The significance of the unity of the historic site and neighboring landscape is focused on by investigating the anaphoric relations between cultural landscape texts('Yeongwol Palgyeong') and historic content(the sad history of King Danjong). For this, the cultural lnddscape of Yeongwol has been framed and layered to make spatial texts. To emphasize the 'Telling' as well as the 'Story,' interesting episodes have been reviewed to discover a motive. To diversify the 'Telling' methods, absorptive landscape factors have been classified as 'Place,' 'Object' and 'Visual Point.' In addition the storytelling of Yeongwol Palgyeong was examined in consideration of the story and background of 'Yeongwol Palgyeong - Sad Story of King Danjong' and the interaction of a variety of cultural content by suggesting micro-content such as infotainment and edutainment as absorptive landscape factors. In order to make the storytelling plan available in practice as an alternative plan for Yeongwol Tourism, a visual point should be properly set to make the landscape look sufficiently dynamic. In addition, real landscape routes and narration scenarios should be prepared as well. Professional landscape interpreters who are well informed of the natural features of Yeongwol and the history of King Danjong should be brought into the project, and Internet and digital technology-based strategies should be developed.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.27 no.12C
• /
• pp.1288-1298
• /
• 2002

To implement elliptic curve cryptosystem in GF(2$\^$m/) at high speed, a fast divider is required. Although bit-parallel architecture is well suited for high speed division operations, elliptic curve cryptosystem requires large m(at least 163) to support a sufficient security. In other words, since the bit-parallel architecture has an area complexity of 0(m$\^$m/), it is not suited for this application. In this paper, we propose a new serial-in serial-out systolic array for computing division operations in GF(2$\^$m/) using the standard basis representation. Based on a modified version of tile binary extended greatest common divisor algorithm, we obtain a new data dependence graph and design an efficient bit-serial systolic divider. The proposed divider has 0(m) time complexity and 0(m) area complexity. If input data come in continuously, the proposed divider can produce division results at a rate of one per m clock cycles, after an initial delay of 5m-2 cycles. Analysis shows that the proposed divider provides a significant reduction in both chip area and computational delay time compared to previously proposed systolic dividers with the same I/O format. Since the proposed divider can perform division operations at high speed with the reduced chip area, it is well suited for division circuit of elliptic curve cryptosystem. Furthermore, since the proposed architecture does not restrict the choice of irreducible polynomial, and has a unidirectional data flow and regularity, it provides a high flexibility and scalability with respect to the field size m.

• Journal of the Korean Institute of Traditional Landscape Architecture
• /
• v.38 no.1
• /
• pp.77-84
• /
• 2020

This study is apply 3D spatial information per traditional landscape space by comparing spatial information data created using a small drone and 3D scanner used for 3D spatial information construction for efficient preservation and management of traditional landscaping space composed of areas such as scenic sites and traditional landscape architectures. The analysis results are as follows. First, aerial photogrammetry data is less accurate than 3D scanners, but it was confirmed to be more suitable for monitoring landscape changes by reading RGB images than 3D scanners by texture mapping using digital data in constructing orthographic image data. Second, the orthographic image data constructed by aerial photogrammetry in a traditional landscaping space consisting of a fixed area, such as Gwanghalluwon Garden, produced visually accurate and precise results. However, as a result of the data extraction, data for trees, which is one of the elements that make up the traditional landscaping, was not extracted, so it was determined that 3D scanning and aerial surveying had to be performed in parallel, especially in areas where trees were densely populated. Third, The surrounding trees in Soswaewon Garden caused many errors in 3D spatial information data including topographic data. It was analyzed that it is preferable to use 3D scanning technology for precise measurement rather than aerial photogrammetry because buildings, landscaping facilities and trees are dense in a relatively small space. When 3D spatial information construction data for a traditional landscaping space composed of area using a small drone and a 3D scanner free from temporal and spatial constraints and compared the data was compared, the aerial photogrammetry is effective for large site such as Hahoe Village, Gyeongju and construction of a 3D space using a 3D scanner is effective for traditional garden such as Soswaewon Garden.

• Journal of Internet Computing and Services
• /
• v.6 no.6
• /
• pp.139-148
• /
• 2005

The desired level for multimedia services in the mobile web environment, the next generation web environment, is expected to be of PC level quality. And great efforts have been made in the development of hadware technology, communication technology, various kinds of services and standardization to support these services, In the mobile web environment, multimedia contents adaptation services should be available through supporting various kinds of devices, network abilities and users' preferences. It means that due to the variety of both desired devices' hardware specifications, called destinations, and desired QoSes, the QoSes in the destinations are not fixed or defined. If a new user wants to stream multimedia contents in a server through a new kind of terminal device, it should be considered whether the existing transcoders are able to adapt the multimedia contents. However, the existing libraries for multimedia adaptation have heavy transcoder figures which include all adaptive functions in one library, The challenge of universal access is too complex to be solved with these all in one solutions. Therefore, in this paper we propose an application independent multimedia adaptation framework which meets the QoS of new and varied mobile devices. This framework is composed of a group of unit transcoders having only one transcoding function respectively, Instead of heavy transcoders. Also, It includes the transcoder manager supporting the dynamic connections of the unit transcoders in order to satisfy end to end QoS.

• Journal of KIISE:Computing Practices and Letters
• /
• v.7 no.3
• /
• pp.240-247
• /
• 2001

Java is a promising runtime environment for embedded systems because it has many advantages such as platform independence, high security and support for multi-threading. One of the most famous Java run-time environments, Sun's ($PersonalJave^{TM}$) is based on Truffle architecture, which enables programmers to design various GUIs easily. For this reason, it has been ported to various embedded systems such as set-top boxes and personal digital assistants(PDA's). Basically, Truffle uses heavy-weight window managers such as Microsoft vVin32 API and X-Window. However, those window managers are not adequate for embedded systems because they require a large amount of memory and disk space. To come up with the requirements of embedded systems, we adopt Microwindows as the platform graphic system for Personal] ava A WT onto Embedded Linux. Although Microwindows is a light-weight window manager, it provides as powerful API as traditional window managers. Because Microwindows does not require any support from other graphics systems, it can be easily ported to various platforms. In addition, it is an open source code software. Therefore, we can easily modify and extend it as needed. In this paper, we implement Personal]ava A WT using Microwindows on embedded Linux and prove the efficiency of our approach.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.42 no.1
• /
• pp.47-55
• /
• 2005

This work describes an 8b 240 MS/s CMOS ADC as one of embedded core cells for high-performance displays requiring low power and small size at high speed. The proposed ADC uses externally connected pins only for analog inputs, digital outputs, and supplies. The ADC employs (1) a two-step pipelined architecture to optimize power and chip size at the target sampling frequency of 240 MHz, (2) advanced bootstrapping techniques to achieve high signal bandwidth in the input SHA, and (3) RC filter-based on-chip I/V references to improve noise performance with a power-off function added for portable applications. The prototype ADC is implemented in a 0.18 um CMOS and simultaneously integrated in a DVD system with dual-mode inputs. The measured DNL and INL are within 0.49 LSB and 0.69 LSB, respectively. The prototype ADC shows the SFDR of 53 dB for a 10 MHz input sinewave at 240 MS/s while maintaining the SNDR exceeding 38 dB and the SFDR exceeding 50 dB for input frequencies up to the Nyquist frequency at 240 MS/s. The ADC consumes, 104 mW at 240 MS/s and the active die area is 1.36 ㎟.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.41 no.1
• /
• pp.53-60
• /
• 2004

This work describes a l0b 150 MSample/s CMOS pipelined A/D converter (ADC) based on advanced bootsuapping techniques for higher input bandwidth than a sampling rate. The proposed ADC adopts a typical multi-step pipelined architecture, employs the merged-capacitor switching technique which improves sampling rate and resolution reducing by $50\%$ the number of unit capacitors used in the multiplying digital-to-analog converter. On-chip current and voltage references for high-speed driving capability of R & C loads and on-chip decimator circuits for high-speed testability are implemented with on-chip decoupling capacitors. The proposed AU is fabricated in a 0.18 um 1P6M CMOS technology. The measured differential and integral nonlinearities are within $-0.56{\~}+0.69$ LSB and $-1.50{\~}+0.68$ LSB, respectively. The prototype ADC shows the signal-to-noise-and-distortion ratio (SNDR) of 52 dB at 150 MSample/s. The active chip area is 2.2 mm2 (= 1.4 mm ${\times}$ 1.6 mm) and the chip consumes 123 mW at 150 MSample/s.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.43 no.12 s.354
• /
• pp.15-22
• /
• 2006

In this paper, 1.8V 8-bit 500MSPS Low-power CMOS Digital-to-Analog Converter(DAC) for UWB(Ultra Wide Band) Communication Systeme is proposed. The architecture of the DAC is based on a current steering 6+2 full matrix type which has low glitch and high linearity. In order to achieve a high speed and good performance, a current cell with a high output impedance and wide swing output range is designed. Further a thermometer decoder with same delay time and low-power switching decoder for high efficiency performance are proposed. The proposed DAC was implemented with TSMC 0.18um 1-poly 6-metal N-well CMOS technology. The measured SFDR was 49dB when the output frequency was 50MHz at 500MS/s sampling frequency. The measured INL and DNL were 0.9LSB and 0.3LSB respectively. The DAC power dissipation was 20mW and the effective chip area was $0.63mm^2$.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.43 no.12 s.354
• /
• pp.47-54
• /
• 2006

This work proposes a dual-channel 6b 1GS/s ADC for ultra wide-band communication system applications. The proposed ADC based on a 6b interpolated flash architecture employs wide-band open-loop track-and-hold amplifiers, comparators with a wide-range differential difference pre-amplifier, latches with reduced kickback noise, on-chip CMOS references, and digital bubble-code correction circuits to optimize power, chip area, and accuracy at 1GS/s. The ADC implemented in a 0.18um 1P6M CMOS technology shows a signal-to-noise-and-distortion ratio of 30dB and a spurious-free dynamic range of 39dB at 1GS/s. The measured differential and integral non-linearities of the prototype ADC are within 1.0LSB and 1.3LSB, respectively. The dual-channel ADC has an active area of $4.0mm^2$ and consumes 594mW at 1GS/s and 1.8V.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.43 no.12 s.354
• /
• pp.55-64
• /
• 2006

This work proposes a calibration-free 14b 70MS/s 0.13um CMOS ADC for high-performance integrated systems such as WLAN and high-definition video systems simultaneously requiring high resolution, low power, and small size at high speed. The proposed ADC employs signal insensitive 3-D fully symmetric layout techniques in two MDACs for high matching accuracy without any calibration. A three-stage pipeline architecture minimizes power consumption and chip area at the target resolution and sampling rate. The input SHA with a controlled trans-conductance ratio of two amplifier stages simultaneously achieves high gain and high phase margin with gate-bootstrapped sampling switches for 14b input accuracy at the Nyquist frequency. A back-end sub-ranging flash ADC with open-loop offset cancellation and interpolation achieves 6b accuracy at 70MS/s. Low-noise current and voltage references are employed on chip with optional off-chip reference voltages. The prototype ADC implemented in a 0.13um CMOS is based on a 0.35um minimum channel length for 2.5V applications. The measured DNL and INL are within 0.65LSB and l.80LSB, respectively. The prototype ADC shows maximum SNDR and SFDR of 66dB and 81dB and a power consumption of 235mW at 70MS/s. The active die area is $3.3mm^2$.