• Title/Summary/Keyword: Digital architecture

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A Simple Design Method of Un-reinforced Masonry Wall (비보강 조적 벽체의 간이 설계법(設計法))

  • Yoon, Myung-Ho;Cho, Byoung-Hoo
    • Journal of The Korean Digital Architecture Interior Association
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    • v.2 no.1
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    • pp.45-51
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    • 2002
  • The masonry structure has been widely used as the dwelling house structure in our country for a long time. The masonry structure is weak in the lateral forces such as strong wind and earthquake. But there is no regulation for it in the domestic aseismic design codes. The purpose of this study is to suggest a simple design method of un-reinforced masonry wall.

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Home Gateway Architecture for Realtime Multimedia Distribution in Home Networking (실시간 멀티미디어의 분배를 위한 홈게이트웨이 구조)

  • 이동욱;이철호;한상우;김종원;조충래;전용일
    • Proceedings of the IEEK Conference
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    • 2003.11a
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    • pp.509-512
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    • 2003
  • On-going convergence between broadcasting and communication is currently bringing in lots of drastic changes to multimedia services to the home. The FTTH-based home networks will be the interface among the digital home appliances for broadcast digital contents as weil as for broadband data connection. In this paper, we discuss several design issues for home gateway architecture that effectively distributes realtime broadcasting contents (from either the headend in the access network or the satellite/terrestrial broadcasts) to heterogeneous devices in the home network.

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Design methodology of digital circuits for an audio-signal-processing DAC (오디오 신호처리용 DAC디지털 단의 설계기법)

  • 김선호;손영철;김상호;이지행;김대정;김동명
    • Proceedings of the IEEK Conference
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    • 2002.06b
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    • pp.157-160
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    • 2002
  • This paper proposed a guideline for selecting the arithmetic circuit architecture. The guideline incorpo-rates the new concept of PDSP (power-delay-size product) and the weighting method. HSPICE simulations havc been performed to several full adders in order to prove the validity of the proposed guideline. We applied this guideline to select an optimized FA (full adder) architecture and successfully implemented the DAC's digital blocks.

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Direct Digital Frequency Synthesizer design using CORDIC algorithm (CORDIC 알고리즘을 이용한 DDFS 설계)

  • 이민석;조원경
    • Proceedings of the IEEK Conference
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    • 1999.11a
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    • pp.985-988
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    • 1999
  • This paper describes the architecture and the IC implementation of a Direct Digital Frequency Synthesizer (DDFS). That is based on an angle rotation algorithm (CORDIC). It is shown that the architecture can be implemented as a multipliers, feedfoward, and easily pipelineable datapath. A prototype IC has been designed, fabricated in 0.35${\mu}{\textrm}{m}$ SAMSUNG KG90 Library.

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The Problems of an Acute Angle Design in Architectural Form and Improvement Plan (건축의 형태에 있어서 예각(銳角) 디자인의 문제점과 개선방안)

  • Lim, Myung-Gu;Lee, Jae-Kook
    • Journal of The Korean Digital Architecture Interior Association
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    • v.3 no.2
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    • pp.20-29
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    • 2003
  • It is an obstacle to improve living environments that an acute angle architectural design is often seen. Though that design give a stress to the neighborhood, we can't prevent the design taking place. We must control architectural design, because it is important to public worth and urban aesthetic. To prevent selfish architectural design, it is recommend to extend design review and reflect neighborhood opinions.

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A Study on Properties of Water on Space (건축공간에서 물(水)의 특성에 관한 연구)

  • Min, Young-Gi
    • Journal of The Korean Digital Architecture Interior Association
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    • v.8 no.1
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    • pp.81-87
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    • 2008
  • This study is primarily concerned with the relationship between the substantial nature of water and water space, defined as the container of water, when water is used as an element of design. In order to achieve the objective set up, the writer discusses the important properties of water. As the functional meaning of 'water' has been changed to the natural harmony or agreement with human, both the exterior shape of architectural structures and their internal meanings should be taken into account, if the water space is to be suitable for humans.

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An implementation of DWT Encoder design for image compression (영상 압축을 위한 DWT Encoder 설계)

  • 이강현
    • Proceedings of the IEEK Conference
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    • 1999.11a
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    • pp.491-494
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    • 1999
  • Introduction of digital communication network such as Integrated Services Digital Networks(ISDN) and digital storage media have rapidly developed. Due to a large amount of image data, compression is the key techniques in still image and video using digital signal processing for transmitting and storing. Digital image compression provides solutions for various image applications that represent digital image requiring a large amount of data. In this paper, the proposed DWT(Discrete Wavelet Transform) filter bank is consisted of simple architecture, but it is efficiently designed that a user obtain a wanted compression rate as only input parameter. If it is implemented by FPGA chip, the designed encoder operates in 12MHz.

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A Study on the Design of Low Power Digital PLL (저전력 디지털 PLL의 설계에 대한 연구)

  • Lee, Je-Hyun;Ahn, Tae-Won
    • 전자공학회논문지 IE
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    • v.47 no.2
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    • pp.1-7
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    • 2010
  • This paper presents a low power digital PLL architecture and design for implementation of the PLL-based frequency synthesizers. In the proposed architecture, a wide band digital logic quadricorrelator is used for preliminary frequency detector and a narrow band digital logic quadricorrelator is used for final DCO control. Also, a circuit technique for reducing leakage current is adopted in order to minimize the standby mode power consumption of the deactivated block. The proposed digital PLL is designed and verified by MyCAD with MOSIS 1.8V $0.35{\mu}m$ CMOS technology, and the simulation results show that the power consumption can be lowered by more than 20%.

A CFG Based Automated Search Method of an Optimal Transcoding Path for Application Independent Digital Item Adaptation in Ubiquitous Environment (유비쿼터스 환경에서 응용 독립적 DIA를 위한 최적 트랜스코딩 경로의 CFG 기반 자동 탐색 방법)

  • Chon Sungmi;Lim Younghwan
    • The KIPS Transactions:PartB
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    • v.12B no.3 s.99
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    • pp.313-322
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    • 2005
  • In order to access digital items in a server via ubiquitous devices, the digital items should be adapted according to the system environment, device characteristics and user preferences. In ubiquitous environment, those device-dependent adaptation requirements are not statically determined and not predictable. Therefore an application specific adaptation mechanism can not be applied to a general digital item adaptation engine. In this paper, we propose an application independent digital item adaptation architecture which has a set of minimal transcoders, transcoding path generator for a required adaptation requirement, and adaptation scheduler. And a CFG based method of finding a sequence of multiple unit transcoders called a transcoding path Is described in detail followed by experimental results.