• Title/Summary/Keyword: Digital Signal Processor(DSP)

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An Implementation of 16-channel DSP System with Ethernet/USB Interface for Acquisition and Analysis (Ethernet/USB 기반 16채널 데이터 수집 및 분석 시스템 구현)

  • 유재현;송형훈;신현경;조성호
    • Proceedings of the IEEK Conference
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    • 2000.09a
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    • pp.505-508
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    • 2000
  • 본 논문에서는 16채널 혹은 8채널의 센서를 통해 들어오는 저주파대역의 아날로그 신호를 수집하고. 수집된 데이터를 실시간으로 처리하기 위한 고속의 신호처리 기능이 결합된 통합 DSP (Digital Signal Processor)시스템을 구현하였다. 구현된 시스템은 휴대가 용이하도록 소형으로 설계되어 있으며 노트북 등의 이동형 장비에 활용되도록 USB 인터페이스를 채택하였으며, 장치간의 네트워크 구성이 가능하도록 Ethernet 인터페이스를 추가하였다 Digital Signal Processor는 Texas Instrument 사의 TMS320C6701 부동소수점 연산방식의 고성능 DSP를 사용하여 16채널의 실시간 신호 분석이 가능하게 하였으며, ICP 센서 구동용 전류 공급부를 내장하여 센서 선택의 폭을 넓히었고, programmable gain amplifier인 PGA202증폭기를 사용하여 입력신호가 작을 경우 최대 1000배, 즉 60dB까지 입력신호를 증폭하여 수집 및 분석할 수 있다. 200kSPS의 샘플링 레이트와 16bit resolution을 가지는 AD976 A/D converter를 사용하여 채널당 0~6kHz의 신호대역폭을 가지며,differential 입력시 8 채널,single ended 입력시 16 채널의 입력 신호의 수집 및 분석이 가능하다. Windows 응용프로그램에서는 사용자가 원하는 입력신호 및 스펙트럼 실시간 분석, 입력신호 기록 및 저장, RPM 측정 및 분석, 외부 트리거 및 레벨 트리거를 이용한 입력신호 제어와 수집된 데이터를 바탕으로 원하는 제어가 가능한 응용프로그램 제작에 활용될 라이브러리가 포함된다.

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Current-Source PWM Inverter Equipped with DSP for Photovoltaic System (DSP를 이용한 태양광 발전 시스템용 전류형 PWM 인버터)

  • 박성준;허권행;강필순;김철우
    • The Transactions of the Korean Institute of Power Electronics
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    • v.7 no.5
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    • pp.437-442
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    • 2002
  • This paper presents a current-source-inverter based on a buck-boost configuration md its application for residential photovoltaic system. The proposed circuit has five switches. Among them, only one switch acts as chopping, and the other determine the polarity of output; therefore, it can reduce the switching loss. Because the input inductor current is operated on the discontinuous conduction mode, high power factor can be achieved without additional input current controller. So the overall system shows a simple structure. The operational modes are analysed in depth, and then it was verified through the experimental results using a 150[W] prototype equipped with digital signal processor TMS320F241.

A DSP Evaluation System with variable Data Acquisition Buffer Architecture for Real Time Signal Processing (실시간 신호처리를 위한 가변구조 Data Acquisition Buffer의 구조를 갖는 DSP평가용 System.)

  • Ahn D. S.;Seo H. S.;Cha I. W.
    • The Journal of the Acoustical Society of Korea
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    • v.8 no.5
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    • pp.95-101
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    • 1989
  • For developing new algorithms or dedicated hardware by using general purpose Digital Signal Processor chip, emulator H/W and simulator S/W are indispensible. But the most of DSP emulators have limitations on H/W flexibility according to their generalized architectures. In this paper, a DSP evaluation system for real time signal processing was developed using TMS 32020. The I/O buffers storing acquisition data of the system were designed to have variable length $(1\sim2048samp1es) &$ sampling frequency $l00\sim8KHz$.

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Implementation of the Audio CODEC for Digital Audio Broadcasting Service (디지털 오디오 방송 서비스를 위한 오디오 코덱의 구현)

  • 장대영;홍진우
    • Journal of Broadcast Engineering
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    • v.6 no.1
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    • pp.66-71
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    • 2001
  • This paper Introduces an implementation of MPEG-2 AAC codec system for digital audio broadcasting. This system consists of the encoder and the decoder. This system includes MPEG-2 system multiplexing and demultiplexing modules for Interfacing to the ETRI-DAB system. Four DSPs are adopted for the encoder and three DSPs for 7he decoder. Each DSP Processes system control. 1/0 control, audio signal processing. multiplexing and demultiplexing. This Paper also discusses some near future estimations relaxed to the DAB system and it\`s services. Currently a stereo audio codec is available but multi-channel audio codec and MPEG-4 audio cosec wall be also Implemented.

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Implementation of the AAC Audio CODEC for Digital Audio Broadcasting (디지털 오디오 방송을 위한 AAC 오디오 코덱 구현)

  • 장대영;홍진우
    • Proceedings of the Korean Society of Broadcast Engineers Conference
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    • 2000.11b
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    • pp.43-48
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    • 2000
  • This paper introduces MPEG-2 AAC codec system fur digital audio broadcasting. This system consists of encoder and decoder, and this system provides MPEG-2 system multiplexing and demultiplexing functions. Four DSPs are adopted fur encoder and three DSPs fur decoder. Each DSP processes system control, I/O control, and audio signal processing, multiplexing and demultiplexing. This paper also discusses about some near future estimations related to DAB system and services. And at the end of this paper describes about future development plans.

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Repetitive Control of Track Following Error in a Hard Disk Drive (하드 디스크 드라이브의 반복 추종 오차 제어)

  • Jeon, Doyoung;Jong, Ilyong
    • Journal of the Korean Society for Precision Engineering
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    • v.13 no.5
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    • pp.131-138
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    • 1996
  • This paper suggests a servo control algorithm to reduce the repeatable tracking error which is not explicitly taken into account in the design of a conventional PID controller of a computer hard disk drive. The robust stability of the repetitive control system with multiplicative modelling error is analyzed, and the controller was implemented using a fixed point DSP(Digital Signal Processor). Experimental results show that the repetitive errors are suppressed effectively by the proposed controller.

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New Non-linear Inverse Quantization Algorithm and Hardware Architecture for Digital Audio Codecs (디지털 오디오 코덱을 위한 새로운 비선형 역 양자화 알고리즘과 하드웨어 구조)

  • Moon, Jong-Ha;Baek, Jae-Hyun;SunWoo, Myung-Hoon
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.33 no.1C
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    • pp.12-18
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    • 2008
  • This paper This paper proposes a new inverse-quantization(IQ) table interpolation algorithm, specialized Digital Signal Processor(DSP) instructions and hardware architecture for digital audio codecs. Non-linear inverse quantization algorithm is representatively used in both MPEG-1 Layer-3 and MPEG-2/4 Advanced Audio Coding(AAC). The proposed instructions are optimized for the non-linear inverse quantization. The proposed algorithm can minimize operational complexity which reduces total computational load. Performance comparisons show a significant improvement of average error. The proposed instructions and hardware architecture can reduce 20% of the instruction counts and minimize computational loads of IQ algorithms effectively compared with existing IQ table interpolation algorithms. Proposed algorithm can implement commercial DSPs.

A Study on Development of App-Based Electric Fire Prediction System (앱기반 전기화재 예측시스템 개발에 관한 연구)

  • Choi, Young-Kwan;Kim, Eung-Kwon
    • Journal of Internet Computing and Services
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    • v.14 no.4
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    • pp.85-90
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    • 2013
  • Currently, the electric fire prediction system uses PIC(Peripheral Interface Controller) for controller microprocessor. PIC has a slower computing speed than DSP does, so its real-time computing ability is inadequate. So with the basic characteristics waveform during arc generation as the standard reference, the comparison to this reference is used to predict and alarm electric fire from arc. While such alarm can be detected and taken care of from a remote central server, that prediction error rate is high and remote control in mobile environment is not available. In this article, the arc detection of time domain and frequency domain and wavelet-based adaptation algorithm executing the adaptation algorithm in conversion domain were applied to develop an electric fire prediction system loaded with new real-time arc detection algorithm using DSP. Also, remote control was made available through iPhone environment-based app development which enabled remote monitoring for arc's electric signal and power quality, and its utility was verified.

Implementation of a G,723.1 Annex A Using a High Performance DSP (고성능 DSP를 이용한 G.723.1 Annex A 구현)

  • 최용수;강태익
    • The Journal of the Acoustical Society of Korea
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    • v.21 no.7
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    • pp.648-655
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    • 2002
  • This paper describes implementation of a multi-channel G.723.1 Annex A (G.723.1A) focused on code optimization using a high performance general purpose Digital Signal Processor (DSP), To implement a multi-channel G.723.1A functional complexities of the ITU-T G.723.1A fixed-point C-code are measures an analyzed. Then we sort and optimize C functions in complexity order. In parallel with optimization, we verify the bit-exactness of the optimized code using the ITU-T test vectors. Using only internal memory, the optimized code can perform full-duplex 17 channel processing. In addition, we further increase the number of available channels per DSP into 22 using fast codebook search algorithms, referred to as bit -compatible optimization.

Development of Learning Board for the Digital Relay Using DSP (DSP를 이용한 학습용 계전기 보드 개발)

  • Ahn, Yong-Jin;Choi, Young-Woo
    • Proceedings of the KIEE Conference
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    • 2002.07a
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    • pp.187-189
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    • 2002
  • A relaying board is developed for the study of digital relay, which is based on Digital Signal Processor(DSP). The present development is capable of understanding and application for digital relay hardware. To support the design of relaying hardware, first A/D convertor MMI and serial port for communication are embedded, and next a booting cables of three types are supplied. More particularly the relaying board that is convinient to test digital relaying algorithm. This paper concludes by implementing the distance relaying algorithm into a relaying board, the hardware test results show practically high performance.

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