• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.6
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• pp.1177-1182
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• 2016

The most industrial instruments for monitoring and control are occurring the extension problem and the external protocol compatibility. In this paper, we developed the boards for the industrial communication monitoring that are able to convert the protocol in various communication between devices and instruments. These are consisted the main board and several sub-board. They can have extension using the main board connection. The sub-board support the each communication method or data transfer. The main board was used the Atmega 2560 Microprocessor of AVR series, and the sub-boards are have the Atmega 256 or Atmega 128 in the AVR series. We have designed to connect the sub-board using placed the 4 RS485 serial slots in the main board. The sub-boards were developed to support the analog and digital I/O. These are able to have monitoring by CAN and Ethernet communication. The experimental results, we obtained good data transfer rate and conversion rate.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.14 no.5
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• pp.2449-2456
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• 2013

The column-oriented database storage is a very advanced model for large-volume data analysis systems because of its superior I/O performance. Traditional data storages exploit row-oriented storage where the attributes of a record are placed contiguously in hard disk for fast write operations. However, for search-mostly datawarehouse systems, column-oriented storage has become a more proper model because of its superior read performance. Recently, solid state drive using MLC flash memory is largely recognized as the preferred storage media for high-speed data analysis systems. In this paper, we introduce fast column-oriented data storage model and then propose a new storage management scheme using a cross compressed replication for the high-speed column-oriented datawarehouse system. Our storage management scheme which is based on two MLC SSD achieves superior performance and reliability by the cross replication of the uncompressed segment and the compressed segment under high workloads of CPU and I/O. Based on the results of the performance evaluation, we conclude that our storage management scheme outperforms the traditional scheme in the respect of update throughput and response time of the column segments.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.41 no.4
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• pp.41-49
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• 2004

In this paper, a design and measurement method for FPGA embedded gigabit-transceiver is presented. Altera's Stratix GX device which is general purpose transceiver called GXB was used for implementing PCI Express transceiver. PCI Express is the generation high performance serial I/O bus used to interconnect peripheral devices. After GXB was set follow by PCI Express specifications, the design has been verified by timing simulation and implemented as hardware. We tested it as follow. First GXB internal digital and analog block test second GXB transmitter signal integrity test called Eye mask test, third GXB high-speed serial I/O buffer and on-chip termination test and the last GXB protocol test. This paper shows all the design and measurement procedure about FPGA embedded gigabit-transceiver.

• Journal of IKEEE
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• v.15 no.4
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• pp.267-273
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• 2011

In hardware design, its stability and reliability are important, because a hardware error can cause serious damages or disaster. To improve stability and reliability, this paper presents the implementation of the hardware verification system using the fault injection method in PC environment. This paper presents a verification platform that can verify hardware system reliably and effectively, through a process to generate faults as well as insert input signals into the actual running system environment. The verification system is configured to connect a PC with a digital I/O card, and it can transmit or receive signals from the target system, as a verifier's intention. In addition, it can generate faults and inject them into the target system. And it can be monitored by displaying the received signals from the target system to the graphical wave signals. We can evaluate its reliability by analyzing the graphical wave signals. In this paper, the proposed verification system has been applied to the FPGA firmware of a nuclear power plant control system. As a result, we found its usefulness and reliability.

• Proceedings of the Korea Contents Association Conference
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• 2008.05a
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• pp.116-120
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• 2008

Smart Camera provides intelligent vision functionalities which can interpret captured video, extract context-aware information and execute a necessary action in real-timeliness in addition to the functionality of network cameras which transmit the compressed acquired videos through networks. Intelligent vision algorithms demand tremendous computations so that real-time processing of computation of intelligent vision algorithms as well as compression and transmission of videos simultaneously is too much burden for a single CPU. Davinci processor of Texas Instruments is a popular ASSP(Application Specific Standard Product) which has dual core architecture of ARM core and DSP core and provides various I/O interfaces as well as networking interface and video acquiring interface necessary for developing digital video embedded applications. In this paper, we report the results of designing and implementing S/W for Davinci-based smart camera. We implement a face detection as an example of vision application and verify the implementation works well. In the future, for the development of a smart camera with more broad and real-time vision functionalities, it is necessary to study about more efficient vision application S/W architecture and optimization of vision algorithms on DSP core of Davichi processor.

• KIISE Transactions on Computing Practices
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• v.21 no.8
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• pp.543-548
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• 2015

Recently, volume of data has been growing dramatically along with the growth of social media and digital devices. However, the existing disk-based distributed file systems have limits to their performance of data processing or data access, due to I/O processing costs and bottlenecks. To solve this problem, the caching technique is being used to manage data in the memory. In this paper, we propose a cache management scheme to handle load balancing in a distributed memory environment. The proposed scheme distributes the data according to the memory size, n distributed environments with different memory sizes. If overloaded nodes occur, it redistributes the the access time of the caching data. In order to show the superiority of the proposed scheme, we compare it with an existing distributed cache management scheme through performance evaluation.

• Journal of KIISE:Computing Practices and Letters
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• v.13 no.4
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• pp.213-225
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• 2007

Flash memory is widely used as a storage device for potable equipments such as digital cameras, MP3 players and cellular phones because of its characteristics such as its large volume and nonvolatile feature, low power consumption, and good performance. However, a block in flash memories should be erased to write because of its hardware characteristic which is called as erase-before-write architecture. The erase operation is much slower than read or write operations. FTL is used to overcome this problem. We compared the performance of the existing FTL algorithms on Windows-based OS. We have developed a tool called FTL APAT in order to gather I/O patterns of the disk and analyze the performance of the FTL algorithms. It is the log buffer scheme with full associative sector translation(FAST) that the performance is best.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.13 no.8
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• pp.1491-1496
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• 2009

This paper presents an digital based input/output interface circuit for controlling and monitoring the Diesel Engine Generator for emergency. In order to monitor and control of the Emergency Diesel Engine Generator, controlling and monitoring circuits need 5 analog input channels, 2 pick-up coil measuring circuits, 10 digital input channels containing Broken Wire Detect function, and 7 relay control signal output channels. This system performs signal processing of input signal taking advantage of simple filter circuit, photo-coupler and comparator circuit at analog input parts, and output signals for main relay is designed acting by double control, so it prevents malfunction completely. And it improves accuracy of speed input signal by applying digital circuit that processes rick-up coil signal.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.38 no.2
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• pp.169-179
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• 2010

Satisfying the same probability of loss of control and essentially two fail operative performance with a triplex computer architecture requires a lot of modification of the conventional redundancy management design techniques, previously employed in quadruplex digital flight control computer. T-50 FCS for triplex redundancy management design applied an advanced digital flight control architecture with an I/O controller which is functionally independent of the digital computer to achieve the same reliability and special failure analysis and isolation schemes for fail operational goals with a triplex configuration. The analysis results indicated that the triplex flight control system is to satisfy the safety requirement utilizing the advanced flight control techniques and the system performance of the implemented flight control system was verified by failure mode effect test.

• Journal of the Institute of Convergence Signal Processing
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• v.5 no.2
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• pp.159-164
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• 2004

This paper proposes a new digital filter implementation which adopts an identical structure at both behavioral and logic level in top-down design. This methodology is based on the observation that multiplication is a form of convolution and carrying, and therefore multiplication is implemented with the same structure as that of a convolution in a recursive manner at the logic level. In order to demonstrate a recursive structure-based FIR digital filter, we select L-tap transposed and systolic FIR filters, and implement them to have a single structure. The proposed filter design becomes regular and modular because of the recursive adoption of a single structure for convolutions, and is very compact in that it needs only two 1-bit I/O ports in addition to significant improvement on hardware complexity without time penalty on the output sequence.