• Journal of the Korean Society for Precision Engineering
• /
• v.22 no.7 s.172
• /
• pp.130-136
• /
• 2005

A new MR cylinder with built-in valves using MR fluid (MR valve) is suggested and fabricated fur fluid control systems. The MR fluid is a newly developed functional fluid whose obvious viscosity is controlled by the applied magnetic field intensity. The MR cylinder is composed of cylinder with small clearance and piston with electromagnet. The differential pressure is controlled by the applied magnetic field intensity. It has the characteristics of simple, compact and reliable structure. The size of MR cylinder and piston has $\varphi30mm\times300mm$ and $\varphi28.5mm\times120mm$ in face size, respectively and 0.8mm in gap length. Through experiments, it was found that the differential pressure is controlled by the applied magnetic field intensity under little influence of the flow rate, which corresponds to a pressure control valve. The differential pressure of 0.47MPa was obtained with the input current of 1.5A. The rising time was 2.3s in step response of a manipulator using the MR cylinder. The effectiveness of the MR cylinder was also demonstrated through the position control.

• Journal of radiological science and technology
• /
• v.35 no.4
• /
• pp.315-319
• /
• 2012

The aim of this study was to develop a signal process circuit for a position sensitive avalanche photodiode detector. The circuit parts consisted of amplification, differential and peak/hold circuit. This research was the baseline to develop highly compact radiation detector. The signal was amplified by an amplification chip and its shape was changed in a differential circuit to minimize the pulse tailing. The peak/hold circuit detect the peak of the signal from the differential circuit and hold the amplitude of the peak for data acquisition. In order to test the intrinsic function of the circuit, the input signal was transmitted from a commercial pulse generator.

• Journal of the Institute of Electronics Engineers of Korea SC
• /
• v.44 no.1
• /
• pp.85-93
• /
• 2007

This paper presents new LVDS I/O circuits with a high noise margin for use in highly parallel I/O environments. The proposed LVDS I/O includes transmitter and receiver parts. The transmitter circuits consist of a differential phase splitter and a output stage with common mode feedback(CMFB). The differential phase splitter generates a pair of differential signals which have a balanced duty cycle and $180^{\circ}$ phase difference over a wide supply voltage variation due to SSO(simultaneous switching output) noises. The CMFB output stage produces the required constant output current and maintains the required VCM(common mode voltage) within ${\pm}$0.1V tolerance without external circuits in a SSO environment. The proposed receiver circuits in this paper utilizes a three-stage structure(single-ended differential amp., common source amp., output stage) to accurately receive high-speed signals. The receiver part employs a very wide common mode input range differential amplifier(VCDA). As a result, the receiver improves the immunities for the common mode noise and for the supply voltage difference, represented by Vgdp, between the transmitter and receiver sides. Also, the receiver produces a rail-to-rail, full swing output voltage with a balanced duty cycle(50% ${\pm}$ 3%) without external circuits in a SSO environment, which enables correct data recovery. The proposed LVDS I/O circuits have been designed and simulated with 0.18um TSMC library using H-SPICE.

• Journal of Korea Society of Industrial Information Systems
• /
• v.21 no.1
• /
• pp.61-70
• /
• 2016

This paper describes a new PMU(parametric measurement unit) design technique for automatic test equipment(ATE). Only one DDA(differential difference amplifier) is used to force the test signals to DUT(device under test), while conventional design uses two or more amplifiers to force test signals. Since the proposed technique does not need extra amplifiers in feedback path, the proposed PMU inherently guarantees stable operation. Moreover, to measure the response signals from DUT, proposed technique also adopted only one DDA amplifier as an IA(instrument amplifier), while conventional IA uses 3 amplifiers and several resistors. The DDA adopted two rail-to-rail differential input stages to handle full-range differential signals. Gain enhancement technique is used in folded-cascode type DDA to get open loop gain of 100 dB. Proposed PMU design enables accurate and stable operation with smaller hardware and lower power consumption. This PMU is implemented with 0.18 um CMOS process and supply voltage is 1.8 V. Input ranges for each force mode are 0.25~1.55 V at voltage force and 0.9~0.935 V at current force mode.

• Journal of the Institute of Electronics Engineers of Korea SC
• /
• v.40 no.3
• /
• pp.117-126
• /
• 2003

This paper proposes a real-time application of Walsh functions which is based on the on-line Walsh transformation and on-line Walsh function's differential operation. In the existing method of orthogonal functions, a major disadvantage is that process signals need to be recorded prior to obtaining their expansions. This paper proposes a novel method of Walsh transformation to overcome this shortcoming. And the proposed method apply to the unknown inputs observer(UIO) design for linear time-invariant dynamical systems

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.26 no.4
• /
• pp.278-283
• /
• 2013

This paper presents a design and fabrication of 0.5 V two stage operational amplifier. The proposed operational amplifier utilizes body-driven differential input stage and self-cascode current mirror structure. Cadence Virtuoso is used for layout and the layout data is verified by LVS through Mentor Calibre. The proposed two stage operational amplifier is fabricated using $0.13{\mu}m$ CMOS process and operation at 0.5 V is confirmed. Measured low frequency small signal gain of operational amplifier is 50 dB, power consumption is $29{\mu}W$ and chip area is $75{\mu}m{\times}90{\mu}m$.

• Journal of Electrical Engineering and Technology
• /
• v.13 no.6
• /
• pp.2187-2195
• /
• 2018

In order to realize the multi-objective control of single-input multi-output nonlinear differential algebraic system (NDAS) and to improve the dynamic characteristics and static accuracy, a design method of nonlinear control with multi-objective feedback (NCMOF) is proposed, the principium of this method to arrange system poles, as well as its nature to coordinate dynamic characteristics and static accuracy of the system are analyzed in detail. Through NCMOF design method, the multi-objective control of the system is transformed into linear space, and then it is effectively controlled under the nonlinear feedback control law, the problem to balance all control objectives caused by less input and more output of the system thus is solved. Applying NCMOF design method to generator excitation system, the nonlinear excitation control law with terminal voltage, active power and rotor speed as objective outputs is designed. Simulation results show that NCMOF can not only improve the dynamic characteristics of generator, but also damp the mechanical oscillation of a generator in transient process. Moreover, NCMOF can control the terminal voltage of the generator to the setting value with no static error under typical disturbances.

• The Transactions of The Korean Institute of Electrical Engineers
• /
• v.59 no.2
• /
• pp.355-358
• /
• 2010

As CMOS technology continues to scale down, signal processing is favorably done in the digital domain, which requires Analog-to-Digital (A/D) Converter to be integrated on-chip. This paper presents a design methodology of 12-bit 1-MS/s Rail-to-Rail fully differential SAR ADC using Deep N-well Switch based on binary search algorithm. Proposed A/D Converter has the following architecture and techniques. Firstly, chip size and power consumption is reduced due to split capacitor array architecture and charge recycling method. Secondly, fully differential architecture is used to reduce noise between the digital part and converters. Finally, to reduce the mismatch effect and noise error, the circuit is designed to be available for Rail-to-Rail input range using simple Deep N-well switch. The A/D Converter fabricated in a TSMC 0.18um 1P6M CMOS technology and has a Signal-to-Noise-and-Distortion-Ratio(SNDR) of 69 dB and Free-Dynamic-Range (SFDR) of 73 dB. The occupied active area is $0.6mm^2$.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.15 no.9
• /
• pp.743-749
• /
• 2002

A 1.5V 70㏈ 100MHz CMOS class-AB complementary operational amplifier is presented. For obtaining the high gain and the high unity gain frequency, the input stage of the amplifier is designed with rail-to-rail complementary differential pairs which are symmetrically parallel-connected with the NMOS and the PMOS differential input pairs, and the output stage is designed to the rail-to-rail class-AB output stage including the elementary shunt stage technique. With this design technique for output stage, the load dependence of the overall open loop gain is improved and the push-pull class-AB current control can be implemented in a simple way. The designed operational amplifier operates perfectly on the complementary mode with 180$^{\circ}$ phase conversion for 1.5V supply voltage, and shows the push-pull class-AB operation. In addition, the amplifier shows the DC open loop gain of 70.4 ㏈ and the unity gain frequency of 102 MHz for $C_{L=10㎊∥}$ $R_{L=1㏁}$ Parallel loads. When the resistive load $R_{L}$ is varied from 1 ㏁ to 1 ㏀, the DC open loop gain of the amplifier decreases by only 2.2 ㏈.a$, the DC open loop gain of the amplifier decreases by only 2.2 dB.

• ETRI Journal
• /
• v.42 no.6
• /
• pp.943-950
• /
• 2020

We propose 8.2-GHz band radar RFICs for an 8 × 8 phased-array frequency-modulated continuous-wave receiver developed using 65-nm CMOS technology. This receiver panel is constructed using a multichip solution comprising fabricated 2 × 2 low-noise amplifier phase-shifter (LNA-PS) chips and a 4ch RX front-end chip. The LNA-PS chip has a novel phase-shifter circuit for low-voltage operation, novel active single-to-differential/differential-to-single circuits, and a current-mode combiner to utilize a small area. The LNA-PS chip shows a power gain range of 5 dB to 20 dB per channel with gain control and a single-channel NF of 6.4 dB at maximum gain. The measured result of the chip shows 6-bit phase states with a 0.35° RMS phase error. The input P1 dB of the chip is approximately -27.5 dBm at high gain and is enough to cover the highest input power from the TX-to-RX leakage in the radar system. The gain range of the 4ch RX front-end chip is 9 dB to 30 dB per channel. The LNA-PS chip consumes 82 mA, and the 4ch RX front-end chip consumes 97 mA from a 1.2 V supply voltage. The chip sizes of the 2 × 2 LNA-PS and the 4ch RX front end are 2.39 mm × 1.3 mm and 2.42 mm × 1.62 mm, respectively.