• Title/Summary/Keyword: Differential Input

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Experimental Study on Tip Clearance Effects for Performance Characteristics of Ducted Fan

  • Raza, Iliyas;Choi, Hyun-Min;Cho, Jin-Soo
    • Proceedings of the Korean Society of Propulsion Engineers Conference
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    • 2009.11a
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    • pp.395-398
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    • 2009
  • Currently, a new generation of ducted fan UAVs (Unmanned Aerial Vehicles) is under development for a wide range of inspection, investigation and combat missions as well as for a variety of civil roles like traffic monitoring, meteorological studies, hazard mitigation etc. The current study presents extensive results obtained experimentally in order to investigate the tip clearance effects on performance characteristics of a ducted fan for small UAV systems. Three ducted fans having different tip clearance gap and with same rotor size were examined under three different yawed conditions of calibrated slanted hot-wire probe. Three dimensional velocity flow fields were measured from hub to tip at outlet of the ducted fan. The analysis of data were done by PLEAT (Phase locked Ensemble Averaging Technique) and three non-linear differential equations were solved simultaneously by using Newton -Rhapson numerical method. Flow field characteristics such as tip vortex and secondary flow were confirmed through axial, radial and tangential velocity contour plots. At the same time, the effects of tip clearance on axial thrust and input power were also investigated by using wind tunnel measurement system. For enhancing the performance of ducted fan, tip clearance level should be as small as possible.

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Comparative Analysis on the Mock-ups' Configuration and Monitoring Protocol System of Advanced Daylighting Systems for Daylighting Experiment - Focused on IEA SHC Task21- (첨단채광시스템 실험용 Mock-Up 모형의 형상 및 모니터링 프로토콜 시스템에 관한 비교분석 - IEA SHC Task21을 중심으로-)

  • Jeong, In-Young;Choi, Sang-Hyun;Kim, Jeong-Tai
    • KIEAE Journal
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    • v.4 no.1
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    • pp.11-20
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    • 2004
  • Innovative daylighting systems in buildings in various climatic zones around the world have been developed under the IEA SHC Task21. The performance assessment were obtained by monitoring the most systems using full-scale test model rooms or actual buildings under real sky conditions. This study aims to analyze the configuration and monitoring system of the nine Mock-up models of the IEA SHC Task21 comparatively. For the purpose, the geometry of the test rooms (length, width, height, window area, glazed area and occupied), reflectance of walls, floor and ceiling, transmittance of glazing (transmittance for hemispherical irradiation, normal irradiation and U-value) were compared. And equipment for measurement (manufacturer, range, calibration, maximum calibration error, cosine response error, fatigue error), and data acquisition system (manufacturer, type, number of differential analogue input channels, A/D converter resolution in bits, data acquisition software) were also analyzed comparatively. Some findings of these experimental methodology of standard monitoring have been proven to be a valuable one for future assessment of advanced daylighting systems in our country.

A Study on the Design of Built-in Current Sensor for High-Speed Iddq Testing (고속 전류 테스팅 구현을 위한 내장형 CMOS 전류 감지기 회로의 설계에 관한 연구)

  • Kim, Hoo-Sung;Park, Sang-Won;Hong, Seung-Woo;Sung, Man-Young
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2004.07b
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    • pp.1254-1257
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    • 2004
  • This paper presents a built-in current sensor(BICS) that can detect defects in CMOS integrated circuits through current testing technique - Iddq test. Current test has recently been known to a complementary testing method because traditional voltage test cannot cover all kinds of bridging defects. So BICS is widely used for current testing. but there are some critical issues - a performance degradation, low speed test, area overhead, etc. The proposed BICS has a two operating mode- normal mode and test mode. Those methods minimize the performance degradation in normal mode. We also used a current-mode differential amplifier that has a input as a current, so we can realize higher speed current testing. Furthermore, only using 10 MOSFETS and 3 inverters, area overhead can be reduced by 6.9%. The circuit is verified by HSPICE simulation with 0.25 urn CMOS process parameter.

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Development of a Pneumatic Actuation System Real-Time Simulator Using a DSP Board and PC (DSP 카드 및 PC에 의한 공압구동장치의 실시간 모의시험기 개발)

  • Lee, Seong-Rae;Shin, Hyo-Pil
    • Journal of Institute of Control, Robotics and Systems
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    • v.6 no.4
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    • pp.320-326
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    • 2000
  • The real-time simulator of a pneumatic actuation system that is composed of differential PWM signal generator, charge solenoid valve, discharge solenoid valve, actuator, load, and rotational potentiometer is developed using a DSP board and a PC. The simulator receives the control signals from the external controller through the A/D converter, updates the state and output variables of the Pneumatic actuation system responding to the input signals every sampling time, and sends out the output signals through the D/A converter in real time. The user can observe the displacements, velocities, pressures, and mass flows representing the operation of pneumatic actuation system through the PC monitor in real time. Also the user can see the moving images between the pistons and rotating arm realistically in real time. The accuracy of the real-time simulator is verified by the good agreement of the real-time simulation results and the experimental results of the pneumatic actuation system.

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Design of 3V a Low-Power CMOS Analog-to-Digital Converter (3V 저전력 CMOS 아날로그-디지털 변환기 설계)

  • 조성익;최경진;신홍규
    • Journal of the Korean Institute of Telematics and Electronics C
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    • v.36C no.11
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    • pp.10-17
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    • 1999
  • In this paper, CMOS IADC(Current-mode Analog-to-Digital Converter) which consists of only CMOS transistors is proposed. Each stages is made up 1.5-bit bit cells composed of CSH(Current-mode Sample-and-Hold) and CCMP(Current Comparator). The differential CSH which designed to eliminate CFT(Clock Feedthrough), to meet at least 9-bit resolution, is placed at the front-end of each bit cells, and each stages of bit cell ADSC (Analog-to-Digital Subconverter) is made up two latch CCMPs. With the HYUNDAI TEX>$0.65\mu\textrm{m}$ CMOS parameter, the ACAD simulation results show that the proposed IADC can be operated with 47 dB of SINAD(Signal to Noise- Plus-Distortion), 50dB(8-bit) of SNR(Signal-to-Noise) and 37.7 mW of power consumption for input signal of 100 KHz at 20 Ms/s.

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OPAMP Design Using Optimized Self-Cascode Structures

  • Kim, Hyeong-Soon;Baek, Ki-Ju;Lee, Dae-Hwan;Kim, Yeong-Seuk;Na, Kee-Yeol
    • Transactions on Electrical and Electronic Materials
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    • v.15 no.3
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    • pp.149-154
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    • 2014
  • A new CMOS analog design methodology using an independently optimized self-cascode (SC) is proposed. This idea is based on the concept of the dual-workfunction-gate MOSFETs, which are equivalent to SC structures. The channel length of the source-side MOSFET is optimized, to give higher transconductance ($g_m$) and output resistance ($r_{out}$). The highest $g_m$ and $r_{out}$ of the SC structures are obtained by independently optimizing the channel length ratio of the SC MOSFETs, which is a critical design parameter. An operational amplifier (OPAMP) with the proposed design methodology using a standard digital $0.18-{\mu}m$ CMOS technology was designed and fabricated, to provide better performance. Independently $g_m$ and $r_{out}$ optimized SC MOSFETs were used in the differential input and output stages, respectively. The measured DC gain of the fabricated OPAMP with the proposed design methodology was approximately 18 dB higher, than that of the conventional OPAMP.

Design of Next Generation Amplifiers Using Nanowire FETs

  • Hamedi-Hagh, Sotoudeh;Oh, Soo-Seok;Bindal, Ahmet;Park, Dae-Hee
    • Journal of Electrical Engineering and Technology
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    • v.3 no.4
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    • pp.566-570
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    • 2008
  • Vertical nanowire SGFETs(Surrounding Gate Field Effect Transistors) provide full gate control over the channel to eliminate short channel effects. This paper presents design and characterization of a differential pair amplifier using NMOS and PMOS SGFETs with a 10nm channel length and a 2nm channel radius. The amplifier dissipates $5{\mu}W$ power and provides 5THz bandwidth with a voltage gain of 16, a linear output voltage swing of 0.5V, and a distortion better than 3% from a 1.8V power supply and a 20aF capacitive load. The 2nd and 3rd order harmonic distortions of the amplifier are -40dBm and -52dBm, respectively, and the 3rd order intermodulation is -24dBm for a two-tone input signal with 10mV amplitude and 10GHz frequency spacing. All these parameters indicate that vertical nanowire surrounding gate transistors are promising candidates for the next generation high speed analog and VLSI technologies.

Design of Low voltage High speed Phase Locked Loop (고속 저전압 위상 동기 루프(PLL) 설계)

  • Hwang, In-Ho;Cho, Sang-Bock
    • Proceedings of the KIEE Conference
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    • 2007.04a
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    • pp.267-269
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    • 2007
  • PLL(Phase Locked Loop) are widely used circuit technique in modern electronic systems. In this paper, We propose the low voltage and high speed PLL. We design the PFD(Phase Frequency Detector) by using TSPC (True Single Phase Clock) circuit to improve the performance and solve the dead-zone problem. We use CP(Charge Pump} and LP(Loop filter) for Negative feedback and current reusing in order to solve current mismatch and switch mismatch problem. The VCO(Voltage controlled Oscillator) with 5-stage differential ring oscillator is used to exact output frequency. The divider is implemented by using D-type flip flops asynchronous dividing. The frequency divider has a constant division ratio 32. The frequency range of VCO has from 200MHz to 1.1GHz and have 1.7GHz/v of voltage gain. The proposed PLL is designed by using 0.18um CMOS processor with 1.8V supply voltage. Oscillator's input frequency is 25MHz, VCO output frequency is 800MHz and lock time is 5us. It is evaluated by using cadence spectra RF tools.

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Differential Responses of Rice Acid Phosphatase Activities and Isoforms to Phosphorus Deprivation

  • Lim, Jeong-Hyun;Chung, Ill-Min;Ryu, Sang-Soo;Park, Myoung-Ryoul;Yun, Song-Joong
    • BMB Reports
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    • v.36 no.6
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    • pp.597-602
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    • 2003
  • Acid phosphatases (APases) play a role in the release of phosphate in organic complexes in soil. We investigated tissue- and isoform-specific responses of APases to phosphorus (P) deficiency in three rice genotypes; Dasan-byeo, Sobi-byeo, and Palawan. The levels of shoot APase activity per protein were similar in the three genotypes. They significantly decreased with P deprivation that was longer than seven days. Root APase activity per protein was two- to three-fold higher in Dasan than in Sobi and Palawan. In all genotypes the APase activity increased in P-deficient plants, but the increase was higher in Sobi and Palawan. After 21 days of P deprivation, secreted APase activity increased more than eight-fold in Dasan and two-fold in Sobi and Palawan. Isoform profiles of shoot and root APases were most diverse in Dasan. The activities of the major isoforms in P-deficient shoots decreased in all three genotypes. Depending on the genotypes, further increases in constitutive isoforms and new induction of one to four isoforms occurred in P-deficient roots. The results indicate that tissue and genotype differences in the response of APase to P deficiency are primarily facilitated by the different responses of the isoforms.

A Mathematical Model Proposed for the Prediction of the Fate of Priority Organic Pollutants Spilled in Streams: Dynamic Simulations and Sensitivity Analysis (하천에 유입된 유독성 유기오염물의 농도분포를 예측하기 위한 수학적 모형의 개발: Dynamic simulations 및 민감도 분석)

  • Ko, Kwang Baik
    • KSCE Journal of Civil and Environmental Engineering Research
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    • v.12 no.2
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    • pp.265-274
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    • 1992
  • A mathematical model was proposed to predict the fate of a priority organic pollutant, anthracene, accidently spilled into a stream. The model consists of 6 differential equations with 5 input variables and 9 rate constants. Volatilization, biodegradation, adsorption/desorption, photodegradation as well as the convective inputs and outputs are included in the model. As a result of a series of dynamic simulations and sensitivity analyses under the given conditions, the concentrations of the organic chemical could be predicted within a detection limit in the stream. It was also suggested that the rate constant for diffusion/transport and adsorption rate constant are the most influential ones for predicting the chemical conentrations in dissolved and particulate phase. The model proposed appears to be a useful tool for assessing chemical spills.

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