• JSTS:Journal of Semiconductor Technology and Science
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• 제10권4호
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• pp.309-315
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• 2010

A fully-differential low-voltage low-power electrocardiogram (ECG) amplifier by using the nonfeedback PMOS pseudo-resistors is proposed. It consists of two operational-transconductance amplifiers (OTA) in series (a preamplifier and a variable-gain amplifier). To make it insensitive to the gate leakage current of the OTA input transistor, the feedback pseudo-resistor of the conventional ECG amplifier is moved to input branch between the OP amp summing node and the DC reference voltage. Also, an OTA circuit with a Gm boosting block without reducing the output resistance (Ro) is proposed to maximize the OTA DC gain. The measurements shows the frequency bandwidth from 7 Hz to 480 Hz, the midband gain programmable from 48.7 dB to 59.5 dB, the total harmonic distortion (THD) less than 1.21% with a full voltage swing, and the power consumption of 233 nW in a 0.13 ${\mu}m$ CMOS process at the supply voltage of 0.7 V.

• 대한전기학회논문지:전력기술부문A
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• 제54권2호
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• pp.61-66
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• 2005

This paper presents a refined protection algorithm of the unfused 22.9kV shunt capacitor banks in grounded wye connection to improve the existing algorithm using the voltage difference method. It is difficult to detect ground faults with arc near the input points or ground faults near the grounding point by the existing algorithm using only the voltage balanced relay. This paper shows that ground faults with arc near the input point can be detected by harmonics analysis of the differential voltage and that it has no impact of harmonics out of nonlinear loads which have the quantitative influence on capacitor banks. Thus the proposed method using harmonics analysis can be a proper detection method. In case of ground faults near the grounding point, an OVGR is being added recently and its validity is verified in this paper. The proposed method is applied to a 22.9kV example system and is verified that the proposed algorithm can detect clearly faults which are not easy to detect by the existing method.

• 전자공학회논문지
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• 제52권3호
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• pp.19-24
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• 2015

본 논문에서는 massive multiple-input multiple-output (MIMO) 기반의 wireless powered communication network (WPCN)에서 에너지 효율을 향상시키기 위한 기지국 안테나 수 최적화 기법을 제안한다. 제안하는 기법은 massive MIMO 시스템의 채널 hardening 특성을 이용하여 채널 이득을 안테나 수에 대한 식으로 근사한다. 그리고 근사화 된 최적화 문제에 편미분을 적용한 후 Lambert-W 함수를 이용하여 최적해를 closed form으로 찾는다. 모의실험을 통해 제안하는 기법의 근사 과정과 최적화 문제를 해결하는 방법이 적절함을 보이고, closed form 해가 exhaustive search 방법으로 찾은 해와 오차가 크지 않음을 확인한다.

• 전력전자학회논문지
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• 제22권4호
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• pp.277-284
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• 2017

For passive power factor correction, the valley fill circuit approach is attractive for low power applications because of low cost, high efficiency, and simple circuit design. However, to vouch for the product quality, two dc-link capacitors in the valley fill circuit should be selected to withstand the peak rectified ac input voltage. The common mode (CM) and differential mode (DM) choke should be used to suppress the electromagnetic interference (EMI) noise, thereby resulting in large size volume product. This paper presents the practical design and implementation of a valley fill flyback converter with reduced dc link capacitors and EMI magnetic volumes. By using the proposed over voltage protection circuit, dc-link capacitors in the valley fill circuit can be selected to withstand half the peak rectified ac input voltage, and the proposed CM/DM choke can be successfully adopted. The proposed circuit effectiveness is shown by simulation and experimentally verified by a 78W prototype.

• 한국광학회지
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• 제4권3호
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• pp.294-300
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• 1993

표면광 마이크로 레잊, heterojunction phototransistor 그리고 저항을 단일 결정으로 성장시켜 집적시킨 NOR와 INVERTER 능동형 광 논리 소자에 대한 동작 특성을 조사하였다. 능동형 광 놀리 소자를 구성하는 개개 소자 중에서, 780 nm에서 발진하는 특정한 AlGaAs 초격자 마이크로 레이저의 미분 양자 효율은 15%로 나타났고, heterojunction phototransistor의 전류 이득은 에미터-컬렉터 전압이 4V이고, 입력 광의 세기가 $50{\mu}W$일 때 57으로 측정되었다. 직렬 저항이 370 ohm인 광 논리 소자의 출력은 입력광세기사 $47{\mu}W$일 때 $57{\mu}W$에서 $0{\mu}W$으로 감소하였다.

• 디지털융복합연구
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• 제10권11호
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• pp.371-376
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• 2012

본 논문에서는 텍스트 영상에 대한 데이터 천이 최소화를 위한 새로운 데이터 코딩기법과 회로를 제안한다. 제안한 회로는 기존의 Modified LVDS(Low Voltage Differential Signaling)의 문제점인 입력되는 데이터간의 동기와 출력되는 데이터간의 동기 문제를 수정한 개선된 MLVDS 회로와 Text image에 대한 천이 최소화를 위한 추가적인 직렬 데이터 코딩 기법인 TMUX 알고리즘으로 한 클럭에 2비트의 신호를 동시에 전송하여 동작 주파수를 줄일 수 있으며, 전자파 장애와 전력 소비를 해결할 수 있다. 시뮬레이션 결과를 통해서 텍스트 영상 데이터 천이 최소화 향상과 입출력간의 동기문제를 보완되었음을 확인하였다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제5권4호
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• pp.276-281
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• 2005

This paper presents a low voltage operating IF QPSK receiver block which is consisted of programmable gain amplifier (PGA) and analog to digital converter. This PGA has 6 bit control and 250MHz bandwidth, $0{\sim}20\;dB$ gain range. Using the proposed PGA architecture (low distortion gain control switch block), we can process the continuous fully differential $0.2{\sim}2.5Vpp$ input/output range and 44MHz carrier with 2 MHz bandwidth signal at 1.8V supply voltage. Using the sub-sampling technique (input freq. is $44{\sim}46MHz$, sampling freq. is 25MHz), we can process the IF QPSK signal ($44{\sim}46MHz$) which is the output of the 6 bit PGA. We can get the SNDR 35dB, which is the result of PGA and ADC at full gain mode. We fabricated the PGA and ADC and the digital signal processing block of the IF QPSK with the 0.18um CMOS MIM process 1.8V Supply.

• 대한전기학회논문지:전력기술부문A
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• 제48권4호
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• pp.461-466
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• 1999

A CMOS op amp with rail-to-rail input and output ranges is designed in a one-volt supply. The output stage of the op amp is used in a common source amplifier that operates in sub-threshold region to design a low voltage op amp with rail-to-tail output range. To drive heavy resistor and capacitor loads with rail-to-rail output ranges, a common source amplifier which has a low output resistance is utilized. A bulk-driven differential pair and a bulk-driven folded cascode amplifier are used in the designed op amp to increase input range and achieve 1 V operation. Post layout simulation results show that low frequency gain is about 58 ㏈ and gain bandwidth I MHz. The designed op amp has been fabricated in a 0.8${\mu}{\textrm}{m}$ standard CMOS process. The measured results show that this op amp provides rail-to-rail output range, 56㏈ dc gain with 1 MΩ load and has 0.4 MHz gain-bandwidth with 130 ㎊ and 1 kΩ loads.

• 드라이브 ㆍ 컨트롤
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• 제13권2호
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• pp.42-50
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• 2016

The conventional technique to measure the hysteresis and the null of servo valves is defined in ISO 10770-1 and based on load flow signal of the servo valve. A new technique based on the transmission line pressures is suggested in this study. The new measuring method was verified through a series of experiments. No hysteresis was observed between the spool displacement and the transmission line pressures, load pressure or each chamber pressure. Some hysteresis was observed between valve input and pressures, which was found to be the same as those of load flow and spool displacement for the valve input. By using the chamber pressures, the hysteresis and the null are easier to measure than the load pressure or differential pressure between those two chamber pressures because the chamber pressures showed sharp edges.

• 센서학회지
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• 제28권4호
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• pp.240-245
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• 2019

Phase interpolation is widely adopted in frequency synthesizers and clock-and-data recovery systems to produce an intermediate phase from two existing phases. The intermediate phase is typically generated by combining two input phases with different weights. Unfortunately, this results in non-uniform phase steps. Alternatively, the intermediate phase can be generated by successive approximation, where the interpolated phase at each approximation stage is obtained using the same weight for the two intermediate phases. As a proof of concept, this study presents a 2-GHz 8-bit successive approximation digital-to-phase converter that is designed using 65-nm CMOS technology. The converter receives an 8-phase clock signal as input, and the most significant bit (MSB) section selects four phases to create two sinusoidal waveforms using a harmonic rejection filter. The remaining least significant bit (LSB) section applies the successive approximation to generate the required intermediate phase. Monte-Carlo simulations show that the proposed converter exhibits 0.46-LSB integral nonlinearity and 0.31-LSB differential nonlinearity with a power consumption of 3.12 mW from a 1.2-V supply voltage.