• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.9
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• pp.714-723
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• 2003

An effective technique to increase the signal swing and reduce noise is to use fully-differential -circuits. However, design of a common-mode feedback (CMFB) circuit that stabilizes the common-mode output level is essential. In this paper, a general description is given to fully-differential amplifiers with their CMFB loops, then a new error amplifier that is just composed of transistors and stabilizes the DC output level is proposed. We designed a simple and efficient bias circuit that allows the stability and maximum input swing. Simulation result shows the enhanced phase margin and increased differential-mode input swing with a proposed error amplifier.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.17 no.3
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• pp.999-1021
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• 2023

Differential spatial modulation uses the antenna index to transmit information, which improves the spectral efficiency, and completely bypasses any channel side information in the recommended setting. A generalized distributed multiple turbo coded-cooperative differential spatial modulation based on distributed multiple turbo code is put forward and its performances in Rayleigh fading channels is analyzed. The generalized distributed multiple turbo coded-cooperative differential spatial modulation scheme is a coded-cooperation communication scheme, in which we proposed a new joint parallel iterative decoding method. Moreover, the code matched interleaver is considered to be the best choice for the generalized multiple turbo coded-cooperative differential spatial modulation schemes, which is the key factor of turbo code. Monte Carlo simulated results show that the proposed cooperative differential spatial modulation scheme is better than the corresponding non-cooperative scheme over Rayleigh fading channels in multiple input and output communication system under the same conditions. In addition, the simulation results show that the code matched interleaver scheme gets a better diversity gain as compared to the random interleaver.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.33 no.2
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• pp.175-182
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• 2023

Differential cryptanalysis is one of the analysis techniques for block ciphers, and uses the property that the output difference with respect to the input difference exists with a high probability. If random data and differential data can be distinguished, data complexity for differential cryptanalysis can be reduced. For this, many studies on deep learning-based neural distinguisher have been conducted. In this paper, a deep learning-based neural distinguisher for PIPO 64/128 is proposed. As a result of experiments with various input differences, the 3-round neural distinguisher for the differential characteristics for 0, 1, 3, and 5-rounds achieved accuracies of 0.71, 0.64, 0.62, and 0.64, respectively. This work allows distinguishing attacks for up to 8 rounds when used with the classical distinguisher. Therefore, scalability was achieved by finding a distinguisher that could handle the differential of each round. To improve performance, we plan to apply various neural network structures to construct an optimal neural network, and implement a neural distinguisher that can use related key differential or process multiple input differences simultaneously.

• Proceedings of the IEEK Conference
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• 2001.06b
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• pp.137-140
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• 2001

This paper shows an asynchronous comparator circuit for 1.2Gbps signal receiver that converts 1.2Gbps data rate input signals with less than 100㎷ swing to on-chip CMOS compatible voltage levels in a 0.35${\mu}{\textrm}{m}$ CMOS process. Folded-cascode nMOS input stage with source-coupled pMOS input stage cover rail-to-rail input common-mode range. Drastic gain-bandwidth increment due to gain-boosting stage with positive-feedback latch as well as wide input common-mode range make designed circuit be suitable for a fully differential signal receiver. HSPICE simulation results show that worst-case sensitivity is less than 20㎷ and maximum propagation delay is 640-psec. And also we verified 3.97㎽ power consumption with 150㎷ differential swing amplitude at 1.2Gbps.

• 한국정보디스플레이학회:학술대회논문집
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• 2002.08a
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• pp.567-570
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• 2002

The LVDS (Low Voltage Differential Signaling) I/O cells, fully compatible with ANSI TIA/ EIA-644 LVDS standard, are designed using a 0.35${\mu}m$ standard CMOS technology. With a single 3V supply, the core cells operate at 1.34Gbps and power consumption of the output driver and the input receiver is 10. 5mW and 4.2mW, respectively. In the output driver, we employ the DCMFB (Dynamic Common-Mode FeedBack) circuit which can control the DC offset voltage of differential output signals. The SPICE simulation result of the proposed output driver shows that the variation of the DC offset voltage is 15.6% within a permissible range. In the input receiver, the proposed dual input stage with a positive feedback latch covers rail-to-rail input common-mode range and enables a high-speed, low-power operation. 5-channels of the proposed LVDS I/O pair can handle display data up to 8-bit gray scale and UXGA resolution.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.56 no.2
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• pp.424-427
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• 2007

A fully differential transconductor using the series composite transistor is proposed. Simulation results show that THD is less than 1.2% for the differential input signal of up to $1.5V_{p-p}$ when the input signal frequency is 10MHz. i he proposed transconductor is used to design a third-order elliptic Gm-C lowpass filter with 138kHz cutoff frequency for ADSL Tx filter. The design procedure is based on signal flow graph(SFG) of a doubly-terminated LC ladder filter by means of fully differential transconductors and capacitors. The filter is fabricated and measured with a $0.35{\mu}m$ CMOS process.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.31B no.3
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• pp.53-59
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• 1994

A new fully differential sample-and-hold circuit which can effectively compensate the offset voltage of an operational amplifier and the charge injection of a MOS switch is presented. The proposed circuit shows a true sample-and-hold function without a reset period or an input-track period. The prototype fabricated using a 1.2$\mu$m double-polysilicon CMOS process occupies an area of 550$\mu$m$\times$288$\mu$m and the error of the sampled ouput is 0.056% on average for 3V input at DC.

• Proceedings of the KIEE Conference
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• 2002.11c
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• pp.517-520
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• 2002

This paper has been studied Operational Amplification Circuit that has high power specification of 90 W is designed. In the input differential amplifier stage, the current source for circuit bias is designed to protect device from high voltage source. the criving state has the voltage gain more than input differential stage. With temperature compensation design, output stage works stable in different to temperature.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.29A no.7
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• pp.82-88
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• 1992

This paper presents one of the first comprehensive studies of how hot electron degradation impacts the input offset voltage of a CMOS differential amplifiers. This study utilizes the concept of a virtual source-coupled MOSFET pair in order to evaluate offset voltaged egradation directly from individual device measurement. Next, analytical models are developed to describe the offset voltage degradation. These models are used to examine how hot electron induced offset voltage is affected with the device parameters.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.12
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• pp.59-65
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• 1998

In this paper, a novel rail-to-rail input stage circuit with improved transconductance Is designed. Its excellent performances over whole common-mode input voltage Vcm range is demonstrated by circuit simulator HSPICE. The novel input stage circuit comprises additional 4 input transistors and 4 current sources/sinks. It maintains DC currents of signal amplifying transistors when one of the differential input stage circuits operates, but it reduces these currents to 1/4 when both differential input stage circuits operates, As a result, a operational amplifier with the novel circuit maintains nearly constant transconductance performance and unity-gain frequency in strong inversion region. The novel circuit allows an optimal frequency compensation and uniform operational amplifier performance over whole Vcm range.