• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.4
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• pp.891-896
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• 2011

This paper describes the differential voltage-to-frequency converter which is realized current conveyor circuits. The output frequency of the differential voltage-to-frequency converter is proportional to the difference of two input voltages. The designed circuit is simulated by HSPICE. The range of input voltage difference is from several volts to several milli-volts. From the simulation results the error is less than from -1.9% to +1.8% compared to the calculated values.

• The Transactions of the Korean Institute of Electrical Engineers A
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• v.49 no.9
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• pp.446-450
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• 2000

A conventional variable percentage current differential relaying algorithm for bus protection may misoperate for external faults with severe CT saturation and internal faults with high impedance. This paper proposes a percentage differential current relaying algorithm for bus protection combined with a compensating algorithm of secondary currents of CTs. Even though CTs are saturated and their secondary currents are severely distorted, the proposed relaying algorithm does not only misoperate for external faults with CT saturation but also detects the internal faults with high fault impedance. Thus, the method improves the sensitivity of the relays and does not require any counterplan for CT saturation.

• Proceedings of the KIEE Conference
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• 2002.07a
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• pp.16-18
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• 2002

This paper proposes a difference-blocked current differential relaying algorithm for power transformers. The proposed algorithm observes that the shape of the differential current is changed using the difference. If the change is detected, output of current differential relay is blocked for a certain time. In this way, the algorithm distinguishes internal faults from magnetizing inrush. The proposed algorithm uses only currents and is unaffected by the remanent flux.

• Proceedings of the KIEE Conference
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• 1999.07c
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• pp.1407-1409
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• 1999

Distance relay is being used for transmission line protection. Recently, current differential relay is used with high reliability in power system. This kind of relay is reported that it has a reliable detection ability, even so high impedance faults take place in transmission line. Therefore it is expected to use and expand widely in many utilities. Tripping of the relay is decided according to the difference between differential and restraint current. However the tripping criterion can be changed by the manufacturers. This paper presents an operational scheme of current differential relay for transmission line protection with graphical model. It is developed for educational purpose for students interesting in power system and protection engineer in utility. MATLAB is used to establish the models.

• The Transactions of the Korean Institute of Electrical Engineers A
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• v.52 no.3
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• pp.158-164
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• 2003

This paper proposes a percentage current differential relaying algorithm for bus protection using an advanced compensating algorithm of the secondary current of current transformers (CTs). The compensating algorithm estimates the core flux at the start of the first saturation based on the value of the second-difference of the secondary current. Then, it calculates the core flux and compensates distorted currents using the magnetization curve. The algorithm Is unaffected by a remanent flux. The simulation results indicate that the proposed algorithm can discriminate internal faults from external faults when the CT saturates. This paper concludes by implementing the algorithm into a TMS320C6701 digital signal processor. The results of hardware implementation are also satisfactory. The proposed algorithm can improve not only stability of the relay in the case of an external fault but sensitivity of the relay in the case of an internal fault.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.6
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• pp.85-96
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• 2000

It is necessary that fully differential operational amplifier circuit should drive an external load in the VLSI design such as SCF(Switched Capacitor Filter), D/A Converter, A/D Converter, Telecommunication Circuit and etc. The conventional CMOS operational amplifier circuit has many problems according to CMOS technique. Firstly, Capacity of large loads are not able to operate well. The problem can be solve to use class AB stages. But large loads are operate a difficult, because an element of existing CMOS has a quadratic functional relation with input and output voltage versus output current. Secondly, Whole circuit of dynamic range decrease, because a range of input and output voltages go down according as increasing of intergration rate drop supply voltage. The problem can be improved by employing fully differential operational amplifier using differential output stage with wide output swing. In this paper, we proposed new current mirror has large output impedance and good current matching with input an output current and compared with characteristics for operational amplifier using cascoded current mirror. To obtain large output swing and low power consumption we suggest a fully differential operational amplifier. The circuit employs an output stage composed new current mirror and two amplifier stage. The proposed circuit is layout and circuit of capability is inspected through simulation program(SPICE3f).

• The Journal of Korean Institute of Communications and Information Sciences
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• v.22 no.4
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• pp.685-695
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• 1997

In this paper, a new CMOS continuous-time fully-differential current-mode integrator is proposed as a basic building block of the low-voltage high frequency current-mode active filter. The proposed integrator is composed of the CMOS complementary circuit which can extend transconductance of an integrator. Therefore, the unity gain frequency which is determined by a small-signal transconductance and a MOSFET gate capacitance can be expanded by the complementary transconductance of the proposed integrator. And also the magnitude of pole and zero are increased. The unity gain frequency of the proposed integrator is increased about two times larger than that of the conventional continuous-time fully-differential integrator with NMOS-gm. These results are verified by the small signal analysis and the SPICE simulation. As an application circuit of the proposed fully-differential current-mode integrator, the three-pole Chebyshev lowpass filter is designed using 0.8.$\mu$m CMOS processing parameters. SPICE simulation predicts a 3-dB bandwidth of 148MHz and power dissipation of 4.3mW/pole for the three-pole filter with 3-V power supply.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.17 no.8
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• pp.867-880
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• 1992

In this paper, a circuit design techniques for Improving the voltage gain of the GaAs MESFET single amplifier is presented. Also, various types of existing current mirror and proposed current mirror of new configuration are compared. To obtain the high differential mode gain and low common mode gain, bootstrap gain enhancement technique Is used and common mode feedback Is employed In the design of differential amplifier. The simulation results show that designed differential amplifier has differential gain of 57.66dB, unity gain frequency of 23.25GHz. Also, differential amplifier using common mode feedback with alternative negative current mirror has CMRR of 83.S8dB, stew rate of 3500 V /\ulcorners.

• Proceedings of the KIEE Conference
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• 1999.07c
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• pp.1139-1141
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• 1999

A variable percentage current differential relaying algorithm is widely used for bus protection. However, it may maloperate in case of high-impedance internal faults and external faults with CT saturation and thus additional method to cope with CT saturation is necessary. This paper proposes a percentage current differential relaying algorithm for bus protection using a compensating algorithm of secondary current of CTs. As the proposed method compensates the distorted secondary currents of CTs it can improves the sensitivity of relays in a large current region and does not need any additional method for CT saturation.

• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.6
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• pp.546-550
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• 2013

We propose a novel negative differential resistance (NDR) device with ultra-high peak-to-valley current ratio (PVCR) by combining pn junction diode with depletion mode nanowire (NW) transistor, which suppress the valley current with transistor off-leakage level. Band-to-band tunneling (BTBT) Esaki diode with degenerately doped pn junction can provide multiple switching behavior having multi-peak and valley currents. These multiple NDR characteristics can be controlled by doping concentration of tunnel diode and threshold voltage of NW transistor. By designing our NDR device, PVCR can be over $10^4$ at low operation voltage of 0.5 V in a single peak and valley current.