• 전기전자학회논문지
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• 제10권2호통권19호
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• pp.141-148
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• 2006

In this study, the design of advanced LVDS(Low Voltage Differential Signaling) I/O interface circuit with new structural low triggering ESD (Electro-Static Discharge) protection circuit was investigated. Due to the differential transmission technique and low signal swing range, maximum transmission data ratio of designed LVDS transmitter was simulated to 5Gbps. And Zener Triggered SCR devices to protect the ESD Phenomenon were designed. This structure reduces the trigger voltage by making the zener junction between the lateral PNP and base of lateral NPN in SCR structure. The triggering voltage was simulated to 5.8V. Finally, The high speed I/O interface circuit with the low triggered ESD protection device in one-chip was designed.

• KEPCO Journal on Electric Power and Energy
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• 제6권4호
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• pp.473-480
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• 2020

In this paper, we proposed a high frequency equivalent circuit considering parasitic impedance components for differential noise analysis on the input stage during DC-DC buck converter switching operation. Based on the proposed equivalent circuit model, we presented a method to measure parasitic impedance parameters included in DC bus plate, IGBT, and PCB track using the gain phase method of a network analyzer. In order to verify the validity of this model, a DC-DC prototype consisting of a buck converter, a signal analyzer, and a LISN device, and then resonance frequency was measured in the frequency range between 150 kHz and 30 MHz. The validity of the parasitic impedance measurement method and the proposed equivalent model is verified by deriving that the measured resonance frequency and the resonance frequency of the proposed high frequency equivalent model are the same.

• 전자공학회논문지B
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• 제31B권3호
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• pp.53-59
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• 1994

A new fully differential sample-and-hold circuit which can effectively compensate the offset voltage of an operational amplifier and the charge injection of a MOS switch is presented. The proposed circuit shows a true sample-and-hold function without a reset period or an input-track period. The prototype fabricated using a 1.2$\mu$m double-polysilicon CMOS process occupies an area of 550$\mu$m$\times$288$\mu$m and the error of the sampled ouput is 0.056% on average for 3V input at DC.

• 한국전자파학회지:전자파기술
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• 제14권1호
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• pp.35-42
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• 2003

Differential signaling has become a popular choice for high-speed interconnection schemes on Printed Circuit Boards (PCBs), offering superior immunity to external noise. However, conventional differential transmission lines on PCBs have problems, such as crosstalk and radiated emission. To overcome these, we propose a Twisted Differential Line (TDL) structure on a multi-layer PCB. Its improved immunity to crosstalk noise and the reduced radiated emission has been successfully demonstrated by measurement. The proposed structure is proven to transmit 3 Gbps digital signals with a clear eye-pattern. Furthermore, it is subject to much less crosstalk noise and achieves a 13 dB suppression of radiated emission. Index Terms - Twisted Differential Line, Differential Signaling, Crosstalk, Radiated Emission, Transmission Line, Twisted Pair

• JSTS:Journal of Semiconductor Technology and Science
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• 제2권1호
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• pp.7-18
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• 2002

Single-ended differential RF circuit topologies fully utilizing complementary characteristics of both NMOS and PMOS are proposed, which have inherent advantage of both single-ended and differential circuits. Using this concept, we propose a CCPP (Complementary CMOS parallel push-pull) amplifier which has single-ended input/output with differential amplifying characteristics, leading to more than 30 dB improvement on $IIP_2$. In addition, complementary resistive mixer is also proposed, which provides not only differential IF outputs from single-ended RF input, but much better linearity as well as isolation characteristics. Experimental results using $0.35{\;}\mu\textrm{m}$ CMOS process show that, compared with conventional NMOS resistive mixer, the proposed mixer shows 15 dB better LO-to-IF isolation, 4.6 dB better $IIP_2$, and 4.5 dB better $IIP_3$performances.

• 한국콘텐츠학회논문지
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• 제6권3호
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• pp.38-45
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• 2006

본 논문은 LCD driver IC의 전송선 당 데이터 전송률을 2배로 하기 위한 이중 저전압 차동신호 전송 (DLVDS) 회로를 제안한다. 제안된 회로에서는 2-비트 데이터를 하나의 송신기에서 입력 받고, 2-비트 데이터를 듀얼레벨을 갖는 차동신호로 전송한다. 따라서 기존의 저전압 차동신호 전송기법(LVDS)의 특징을 유지하면서 2-비트 데이터를 2개의 전송선을 통하여 전송할 수 있다. 제안된 송신기는 전류원 피드백 회로를 이용하여 출력의 공통모드 바이어스 흔들림을 보상했다. 그리하여 기존의 회로의 입력 바이어스와 기준 바이어스 전압 차이로 출력의 공통모드 바이어스 흔들림이 발생하는 문제가 해결되었다. 수신기에서는 디코드 회로를 통해 원래의 2-비트 입력 데이터를 복원할 수 있다. 제안된 회로는 $0.25{\mu}m$ CMOS 공정으로 설계하였고, 시뮬레이션 결과 1-Gbps/2-line의 전송률을 갖고, 2.5V의 전원에서 35-mW의 전력소모를 나타냈다.

• 한국산학기술학회논문지
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• 제22권4호
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• pp.10-16
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• 2021

본 연구에서는 신축성 인덕터를 이용한 센서 응용을 위한 상태 감지 회로로써 패리티-시간 대칭 구조를 고려한 모델을 제안하고자 한다. 신축성 인덕터를 이용한 센서 구동 회로로써 트랜지스터를 이용한 부성 미분 저항 회로를 적용하여 신축성 인덕터를 보다 효율적으로 활용할 수 있는 방법을 제안하고, 패리티-시간 대칭 구조의 결합 공진 회로에 대한 특성 분석을 통해 고전적 공진 회로에 비해 향상된 분해능을 갖는 모델을 설계하였다. 특히, 보다 실질적인 전산모의실험결과를 얻기 위해, 신축성 인덕터 모델의 경우에는 참고문헌의 실험결과를 참고하여 본 연구 모델에 적용하였다. 전산모사를 통해 본 연구에서 사용한 부성 미분 저항 회로를 통해 저항 성분 뿐만 아니라 위상 성분도 제어됨을 확인하였으며, 이러한 결과를 통해 신축성 인덕터의 특성 변화에 따른 회로의 불균형을 부성 미분 저항 회로를 이용하여 보완할 수 있음을 고찰하였다. 이러한 특성을 이용하여 패리티-시간 대칭 구조를 구현할 수 있었으며, 이에 대한 특성에 대하여 논의하였다. 특히, 본 연구에서 제안하는 패리티-시간 대칭 구조의 센서 구동 회로에 대한 주파수 특성의 결과로부터 기존의 고전적 공진 회로에 비해 Q-factor가 최대 20배까지 커질 수 있음을 확인하였다.

• 한국정보통신학회논문지
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• 제15권4호
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• pp.891-896
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• 2011

이 논문에서는 전류 컨베이어 회로를 이용하여 입력 전압의 차에 비례하는 주파수 신호를 생성하는 회로를 설계하였다. 설계된 회로는 HSPICE를 이용하여 회로의 동작을 분석하였으며, 입력 전압 차는 수V에서 수mV 단위까지 변화시키면서 출력 주파수를 시뮬레이션하였다. 회로의 시뮬레이션 결과 이론적인 계산값과 비교하였을 때 에러는 -1.9%에서 +1.8% 이내였다.

• Journal of information and communication convergence engineering
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• 제9권1호
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• pp.11-15
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• 2011

A Differential line inductor is proposed for a differential power amplifier. The proposed differential line inductor is composed of two conventional line inductors rearranged to make the current direction of the two line inductors identical. The proposed line inductor is simulated with a 2.5-D and a 3-D EM simulator to verify its feasibility with the substrate information in a 0.18-${\mu}m$ RF CMOS process. The inductances of various line inductors implemented with printed circuit boards were measured. The feasibility of the proposed line inductor was successfully demonstrated.

• 유공압시스템학회논문집
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• 제5권1호
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• pp.13-19
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• 2008

The typical hydraulic system of hoist is composed of a hydraulic supply unit, a directional control valve, counter balance valve, and flow control valves. The flow capacity coefficients of flow control valves should be adjusted so that the hoist is operated at moderate speed and the hydraulic energy loss is minimized. However, it is difficult to adjust the flow coefficients of flow control valves by trial and error for optimal operation. Here, the steady state model of the hoist hydraulic system including the differential cylinder circuit is derived and the optimal flow capacity coefficients of flow control valves are obtained using the complex method that is one kind of constrained direct search method.