• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.12 no.5
• /
• pp.879-886
• /
• 2008

This paper addresses the analysis and the design optimization of differential interconnects for Low-Voltage Differential Signaling (LVDS) applications. Thanks to the differential transmission and the low voltage swing, LVDS offers high data rates and improved noise immunity with significantly reduced power consumption in data communications, high-resolution display, and flat panel display. We present an improved model and new equations to reduce impedance mismatch and signal degradation in cascaded interconnects using optimization of interconnect design parameters such as trace width, trace height and trace space in differential flexible printed circuit board (FPCB) transmission lines. We have carried out frequency-domain full-wave electromagnetic simulations, time-domain transient simulations, and S-parameter simulations to evaluate the high-frequency characteristics of the differential FPCB interconnects. The 10% change in trace width produced change of approximately 6% and 5.6% in differential impedance for trace thickness of $17.5{\mu}m$ and $35{\mu}m$, respectively. The change in the trace space showed a little change. We believe that the proposed approach is very helpful to optimize high-speed differential FPCB interconnects for LVDS applications.

• Journal of the Korea Computer Industry Society
• /
• v.8 no.2
• /
• pp.123-130
• /
• 2007

In this paper, the design requirement and the electrical circuit analysis are performed to construct the multi-channel cardiac activation pre-amplifier necessary for a signal conditioning circuit. The general 64 channel configuration is expanded into 128 channels to enhance the spatial resolution on the mapped surface of the heart. The 128 channels pre-amplifier consists of input circuit, differential amplifier, right leg driven circuit and main-amplifier with notch filter part.

• Journal of the Semiconductor & Display Technology
• /
• v.15 no.2
• /
• pp.55-60
• /
• 2016

This study was developed through the secondary battery module charging/discharger possible utilization in the production process equipment circuit. The developed module is ensuring construction of efficient and productive charging and discharger through this research a limit on the yield and the price of existing single -channel charge and discharger circuit as a 5V 70A grade secondary battery Formation charge and discharger for up to 1 board 4 channels. In order to improve the sensing accuracy, through a robust differential amplifier circuit described using 16bit Analog-Digital Converter and noise was secured 16bit resolution sensing. The configuration also made demands for property Rise / Fall Time. Data Acquisition, discharge efficiency and also to fit the sink circuit temperature level for mass production.

• Journal of Electrical Engineering and Technology
• /
• v.7 no.2
• /
• pp.221-224
• /
• 2012

We propose a Readout Integrated Circuit (ROIC), which applies a fixed current bias sensing method to the input stage in order to simplify the circuit structure and the infrared sensor characteristic control. For the sample-and-hold stage to display and control a signal detected by the infrared sensor using a two-dimensional (2D) focal plane array, a differential delta sampling (DDS) circuit is proposed, which effectively removes the FPN. In addition, the output characteristic is improved to have wider bandwidth and higher gain by applying a two-stage variable gain amplifier (VGA). The output characteristic of the proposed device was 23.91 mV/$^{\circ}C$, and the linearity error rate was less than 0.22%. After checking the performance of the ROIC using HSPICE simulation, the chip was manufactured and measured using the SMIC 0.35 um standard CMOS process to confirm that the simulation results from the actual design are in good agreement with the measurement results.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.17 no.8
• /
• pp.867-880
• /
• 1992

In this paper, a circuit design techniques for Improving the voltage gain of the GaAs MESFET single amplifier is presented. Also, various types of existing current mirror and proposed current mirror of new configuration are compared. To obtain the high differential mode gain and low common mode gain, bootstrap gain enhancement technique Is used and common mode feedback Is employed In the design of differential amplifier. The simulation results show that designed differential amplifier has differential gain of 57.66dB, unity gain frequency of 23.25GHz. Also, differential amplifier using common mode feedback with alternative negative current mirror has CMRR of 83.S8dB, stew rate of 3500 V /\ulcorners.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.41 no.11
• /
• pp.35-42
• /
• 2004

A CMOS folding ADC with transistor differential pair folding circuit for low power consumption and high speed operation is presented in this paper. This paper explains the theory of transistor differential pair folding technique and many advantages compared with conventional folding and interpolation circuits. A ADC based on transistor differential pair folding circuit uses 16 fine comparators and 32 interpolation resistors. So it is possible to achieve low power consumption, high speed operation and small chip size. Design technology is based on fully standard 0.25${\mu}{\textrm}{m}$ double poly 2 metal n-well CMOS process. A power consumption is 45mW at 2.5V applied voltage and 250MHz sampling frequency. The INL and DNL are within $\pm$0.15LSB and $\pm$0.15LSB respectively. The SNDR is approximately 50dB at 10MHz input frequency.

• Journal of the Korean Institute of Telematics and Electronics
• /
• v.26 no.11
• /
• pp.1666-1671
• /
• 1989

A novel switched-capacitor circuit for interfacing capacitive microtransducers with a digital system is developed based on the dual-slope integration. It consists of a differential integrator and a comparator. Driven by the teo phase clock, the circuit first senses the capacitance difference between the transducer and the reference capacitor in the form of charge, and accumulates it into the feedback capabitor of the integrator for a fixed period of time. The resulant accumulated charge is next extracted by the known reference charge until the integrator output voltage refurns to zero. The length of time required for the integrator output to return to zero, as measured by the number of clock cycle gated into a counter is proportional to the capacitance difference, averaged over the integration period. The whole operation is insensitive to the reference voltage and the capacitor values involved in the circuit, Thus the proposed circuit permits an accurate differental capacitance measurement. An error analysis has showh that the resolution as high as 8 bits can be expected by realizing the circuit in a monolithic MOS IC form. Besides the accuracy, it features the small device count integrable onto a small chip area. The circuit is thus particularly suitadble for the on-chip interface.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.35 no.2
• /
• pp.143-148
• /
• 2022

For the purpose of treating health checkups and recovery of patients in a super-aged society, hospitals use devices designed with a reduction circuit of electromagnetic waves associated with the specific absorption rate of electromagnetic waves absorbed by the human body. In this paper, we proposed a filter improvement design method capable of reducing electromagnetic waves. As a result of confirming the validity of the proposed technique through simulation and experimental results, the following result values were obtained. Applying the common-mode (CM) inductor 4 mH to a calibration circuit, noise decreased in a multiband spectrum. Using the differential mode(DM) inductor 40 µH element in the primary calibration circuit, the noise decreased by 15 dB or more in the 3 MHz band spectrum. Also, applying the Admittance Capacitance (Y-Cap) 10 nF element in the secondary calibration circuit resulted in the decrease by more than 30 dB in the band spectrum before 2 MHz. After using a common-mode inductor 4 mH element in the tertiary calibration circuit, it decreased by more than 15 dB in the band spectrum after 2 MHz.

• Proceedings of the IEEK Conference
• /
• 2003.07b
• /
• pp.979-982
• /
• 2003

Due to the differential transmission technique and low voltage swing, LVDS has been widely used for high speed transmission with low power consumption. This paper presents the design and implementation of interface circuits for 1.5Gb/s operation in 0.35um CMOS technology. The interface circuit ate fully compatible with the low-voltage differential signaling(LVDS) standard. The LVDS proposed in this paper utilizes a sense amplifiers instead of the conventional differential pre-amplifier, which provides a 1.5Gb/s transmission speed with further reduced driver output voltage. Furthermore, the reduced driver output voltage results in reducing the power consumption.

• ETRI Journal
• /
• v.34 no.4
• /
• pp.518-526
• /
• 2012

This paper proposes LC voltage-controlled oscillator (VCO) phase-locked loop (PLL) and ring-VCO PLL topologies with low-phase noise. Differential control loops are used for the PLL locking through a symmetrical transformer-resonator or bilaterally controlled varactor pair. A differential compensation mechanism suppresses out-band spurious tones. The prototypes of the proposed PLL are implemented in a CMOS 65-nm or 45-nm process. The measured results of the LC-VCO PLL show operation frequencies of 3.5 GHz to 5.6 GHz, a phase noise of -118 dBc/Hz at a 1 MHz offset, and a spur rejection of 66 dBc, while dissipating 3.2 mA at a 1 V supply. The ring-VCO PLL shows a phase noise of -95 dBc/Hz at a 1 MHz offset, operation frequencies of 1.2 GHz to 2.04 GHz, and a spur rejection of 59 dBc, while dissipating 5.4 mA at a 1.1 V supply.