• 대한기계학회:학술대회논문집
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• 대한기계학회 2001년도 춘계학술대회논문집A
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• pp.286-291
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• 2001

Applications of bonded dissimilar materials such as IC package, ceramic/metal and resin/metal bonded joints, are very increasing in various industry fields. It is very important to analyze the thermal stress and stress singularity at interface edges in bonded joints of dissimilar materials. In orer to understand the package crack emanating from the edge of Die pad and Resin, fracture mechanics of bonded dissimilar materials and material properties are obtained. In this paper, the thermal stress and its singularity index for the IC package were analyzed using 2-dimensional elastic boundary element method. Crack propagation angle and path by thermal stress were numerically simulated with boundary element method.

• 한국자동차공학회논문집
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• 제16권3호
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• pp.15-22
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• 2008

Applications of bonded dissimilar materials such as integrated circuit(IC) packages, ceramics/metal and resin/metal bonded joints, are very increasing in various industry fields. It is very important to analyze the thermal stress and stress singularity at interface edge in bonded joints of dissimilar materials. In order to investigate the IC package crack propagating from the edge of die pad and resin, the fracture parameters of bonded dissimilar materials and material properties are obtained. In this paper, the thermal stress and its singularity index for the IC package were analyzed using 2-dimensional elastic boundary element method(BEM). From these results, crack propagation direction and path by thermal stress in the IC package were numerically simulated with boundary element method.

• 한국산업융합학회 논문집
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• 제2권2호
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• pp.131-137
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• 1999

Package crack caused by the soldering process in the surface mounting plastic package is evaluated by applying the energy release rate criterion. The package crack formation depend on various parameters such as chip set, chip size, package thickness, package width, material properties and the moisture content etc. The effects of chip set and the other parameters were estimated during the analysis of package cracks which were located in the edge of the upper interface of the chip and the lower interlace of the die pad. From the results, it could be obtained that the more significant parameters to effect the chip set are chip width.

• 한국공작기계학회:학술대회논문집
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• 한국공작기계학회 1999년도 춘계학술대회 논문집
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• pp.117-122
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• 1999

An objective of this study is that when the steel sheet for automobiles would be sheared by using shearing machine, it is to design the forms of pad for obtaining the precision shearing surface to satisfy the conditions required to laser beam butt welding for processed sheared surface and to establish the appropriate condition against the size of gap between strength of pressure and location and clearance between punch and die. For doing so, we will attempt to make a precision of the most possibility of shearing machine by the shearing machine in analyzing the characteristics of the shearing working upon analyzing and clarifying the interrelation among these.

• 한국공작기계학회논문집
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• 제16권6호
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• pp.94-102
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• 2007

Applications of bonded dissimilar materials such as large scale integration (LSI) packages, ceramics/metal and resin/metal bonded joints, are very increasing in various industry fields. It is very important to analyze the thermal stress and stress singularity at interface edge in LSI. In order to investigate stress singularities on the bonded interface edges and delamination of die pad and resin in the IC package. In this paper, stress singularity factors(${\Gamma}_i$) and stress intensity factors($K_i$) considering thermal stress in the IC package were analyzed by using the 2-dimensional elastic boundary element method(BEM).

• Journal of Welding and Joining
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• 제17권2호
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• pp.61-65
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• 1999

Because of the need for packages which accommodate high pin count, high density and high speed device, PBGA(plastic ball grid array) package gets more spotlight. But the substrate material which is used for PBGA package is in nature susceptible to moisture penetration. The objective of the study is to find out the path of delamination in the stacked structure of substrate. To increase the adhesion between the cooper laminate and PSR(photo solder resist) which is the weakest part, experiments were performed by changing parameters of printing pre-treatment and post-treatment process. As a result of experiments, the factor effects on the adhesion between the cooper laminate and PSR is caused by all of the pre-treatment and post-treatment condition. A considerable change was observed depending on the amount of UV irradiation after thermal cure which is typical of printing post-treatment condition rather than pre-treatment condition.

• Design & Manufacturing
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• 제14권2호
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• pp.14-20
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• 2020

In OLED panel production process, it is necessary to cut a part of protective film as a preprocess for lighting inspection. The current method is to recognize only the fiducial mark of the cut-out panel. Bare Glass Cutting does not compensate for machining cumulative tolerances. Even though process defects still occur, it is necessary to develop technology to solve this problem because only the Align Mark of the panel that has already been cut is used as the reference point for alignment. There is a lot of defective lighting during panel lighting test because the correct protective film is not cut on the panel power and signal application pad position. In laser cutting process to remove the polarizing film / protective film / TSP film of OLED panel, laser processing is not performed immediately after the panel alignment based on the alignment mark only. Therefore, in this paper, we performed real time inspection which minimizes the mechanism tolerance by correcting the laser cutting path of the protective film in real time using Machine Vision. We have studied calibration algorithm of Vision Software coordinate system and real image coordinate system to minimize inspection resolution and position detection error and edge detection algorithm to accurately measure edge of panel.

• ETRI Journal
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• 제39권6호
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• pp.866-873
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• 2017

We propose a multilayered-substrate-based power semiconductor discrete device package for a low switching loss and high heat dissipation. To verify the proposed package, cost-effective, low-temperature co-fired ceramic, multilayered substrates are used. A bare die is attached to an embedded cavity of the multilayered substrate. Because the height of the pad on the top plane of the die and the signal line on the substrate are the same, the length of the bond wires can be shortened. A large number of thermal vias with a high thermal conductivity are embedded in the multilayered substrate to increase the heat dissipation rate of the package. The packaged silicon carbide Schottky barrier diode satisfies the reliability testing of a high-temperature storage life and temperature humidity bias. At $175^{\circ}C$, the forward current is 7 A at a forward voltage of 1.13 V, and the reverse leakage current is below 100 lA up to a reverse voltage of 980 V. The measured maximum reverse current ($I_{RM}$), reverse recovery time ($T_{rr}$), and reverse recovery charge ($Q_{rr}$) are 2.4 A, 16.6 ns, and 19.92 nC, respectively, at a reverse voltage of 300 V and di/dt equal to $300A/{\mu}s$.

• Tribology and Lubricants
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• 제12권4호
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• pp.18-27
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• 1996

An interlaboratory wear testing was performed in order to understand the friction behaviors and the wear mechanisms of the sintered composites. The specimens were the sintered bronze matrix composites having various contents of friction additives, friction control agents and reinforcements. The variation of the wear characteristics according to the constituents of the composites as well as the wear conditions was investigated by SEM, EPMA, OM, the hardness testing and the measurement of friction. The specimen having glass fiber as the matrix reinforcement showed a remarkable increase in wear resistance as increasing the content of glass fiber. Graphite particles in the composites exhibited the lubricating effect and also resulted in the lowering strength of the matrix. Addition of Mo powder to the composites led to the deterioration of wear properties at the room temperature, however, an enhanced wear properties were obtained in the containing Mo at an elevated temperature.

• JSTS:Journal of Semiconductor Technology and Science
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• 제9권2호
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• pp.85-90
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• 2009

This paper presents a single supply PLC SoC ASIC with a built-in analog Front-end circuit. To achieve the low power consumption along with low cost, this PLC SoC employs fully CMOS Analog Front End (AFE) and several LDO regulators (LDOs) to provide the internal power for Logic Core, DAC and Input/output Pad driver. The receiver part of the AFE consists of Pre-amplifier, Gain Amplifier and 1 bit Comparator. The transmitter part of the AFE consists of 10 bit Digital Analog Converter and Line Driver. This SoC is implemented with 0.18 ${\mu}m$ 1 Poly 5 Metal CMOS Process. The single supply voltage is 3.3 V and the internal powers are provided using LDOs. The total power consumption is below 30 mA at stand-by mode to meet the Eco-Design requirement. The die size is 3.2 $\times$ 2.8 $mm^{2}$.