• Journal of the Microelectronics and Packaging Society
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• v.13 no.4
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• pp.1-7
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• 2006

A major failure mode for wafer level chip size package (WLCSP) is thermo-mechanical fatigue of solder joints. The mechanical strains and stresses generated by the coefficient of thermal expansion (CTE) mismatch between the die and printed circuit board (PCB) are usually the driving force for fatigue crack initiation and propagation to failure. In a WLCSP process peripheral or central bond pads from the die are redistributed into an area away using an insulating polymer layer and a redistribution metal layer, and the insulating polymer layer affects solder joints reliability by absorption of stresses generated by CTE mismatch. In this study, several insulating polymer materials were applied to WLCSP to investigate the effect of insulating material. It was found that the effect of property of insulating material on WLCSP reliability was altered with a solder ball layout of package.

• Journal of the Korean Society for Precision Engineering
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• v.25 no.10
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• pp.115-121
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• 2008

This paper presents bisymmetric dual iron core lineal motor stage for heavy-duty high precision applications such as large area micro-grooving machines or high precision roll die machines. In this stage, two iron core linear motors are installed in laterally symmetric way to cancel out the attractive forces. Main focus was given to analyzing the effect of cogging force and moment for two different layouts, which are symmetric and half-pitch shifted ones. Experimental results showed that the symmetric layout is more adequate for high precision applications because of its clear moment cancellation effect. It was also verified that the effect of the residual cogging moment can be suppressed further by increasing the bearing stiffness. One problem of the symmetric layout is added cogging force which hinders smooth motion, but its effect was relatively small compared with that of moment cancellation.

• International Journal of Precision Engineering and Manufacturing
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• v.5 no.1
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• pp.36-41
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• 2004

The blanking of thin sheet metal using progressive dies is an important process on production of precision electronic machine parts such as IC leadframe. This paper summarizes the results of simulating the progressive blanking process by means of LS/DYNA. In order to verify the influence of blanking order on the final lead profile and deformed configuration, simulation technique has been proposed and analyzed using a commercial FEM code, LS/DYNA. The results of FE-simulations are in good agreement with the experimental result. After then, to construct rule base in progressive blanking process, FE-simulation has been performed using a simple model. Based on this result rule base is set up and then the blanking order of inner lead is rearranged. Consequently, from the results of FE-simulation using suggested method in this paper, it is possible to predict the shift of lead to manufacture high precision lead frame in progressive blanking process. The proposed method can give more systematic and economically feasible means for designing progressive blanking process.

• Proceedings of the KAIS Fall Conference
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• 2010.11b
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• pp.929-932
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• 2010

플런저(Plunger)의 부품 용도는 점화 플러그와 조립 되는 부품으로 연료 분사장치에 적용하여 연료 효율이 약 15~20% 개선됨이 일본에서 검증되어 일본은 상용화 되었다. 국내에서는 개발단계로 처음에 냉간단조로 개발하였다가 원가 및 생산성 문제로 프로그레시브금형(Progressive Die)로 개발 하려는 단계이다. 디젤기관에 사용되며 기관의 출력을 조절하기 위해 플런저를 이용하여 연료의 토출량을 조절할 때 사용이 된다. 이에 본 논문에서는 디젤 차량에 장착되는 플런저를 냉간단조방식이 아닌 원가 및 생산성을 확보할 수 있는 프로그레시브 금형에 적용하여 양산할 수 있는 스트립 레이아웃을 개발하고자 하였다.

• Proceedings of the KAIS Fall Conference
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• 2011.12b
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• pp.607-610
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• 2011

본 논문은 하이브리드 자동차 및 전기자동차의 고주파 발생시 전자파를 차단하는 역할을 하는 인버터 실드쉘의 단공정 스트립 레이아웃과 금형제작에 관한 연구이다. 현재는 일본에서 금형을 수입하여 7벌 단공정 금형방식으로 개발하여 65톤 프레스에서 시험생산하고 있는 중이다. 이에 본 논문에서는 단공정 금형의 스트립 레이아웃을 분석하여 프로그레시브금형설계 및 제작시 원가경쟁력을 갖추기 위하여 연구하였다.

• 제어로봇시스템학회:학술대회논문집
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• 1991.10a
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• pp.793-798
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• 1991

Implementation of AGVS (Automated Guided Vehicle System) in CIMS (Computer Integrated Manufacturing System) generally requires substantial study to optimize design and performance of the guide path. Traditional mathematical approaches have been used with limited success to analyze AGVS. These approaches, however, do not provide a practical opportunity to use by path designers. This paper presents a new approach based on Jules in designing and assessing AGV path to have better design of the closed-loop layout. A framework for the approach is proposed and a case study is reported to demonstrate the framework. Deletion of seldom used paths and addition of bypasses to solve the congestion problem are conducted automatically through simulation expefiments. To visualize die results a graphic control program is developed and integrated with AutoMod/AutoGram simulation package.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.11
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• pp.152-161
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• 1996

This paper descrisbes the implementation of a 20D DCT that can be used for video conference, JPEG, and MPEG-related applications. The implemented DCT consists of two 1-D DCTs and a transposed memory between them, and uses ROM-based multipliers instead of conventional ones. As the system bit length, the minimum bit length that satisfies the accuracy specified by the ITU standard H.261 was chosen through the simulations using the C language. The proposed design uses a dual port RAM for the transposed memory, and processes two bits of input-pixel data simultaneously t ospeed up addition process using two sets of ROMs. The basic system architecture was designed using th Synopsys schematic editor, and internal modules were described in VHDL and synthesized to logic level after simulation. Then, the compass silicon compiler was used to create the final lyout with 0.8um CMOS libraries, using the standard cell approach. The final layout contains about 110, 000 transistors and has a die area of 4.68mm * 4.96mm, and the system has the processing speed of about 50M pixels/sec.

• 한국금형공학회:학술대회논문집
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• 2008.06a
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• pp.89-94
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• 2008

The injection molding process is a predominant method for producing plastic parts. In order to maximize productivity and molding quality in a injection mold, it is important that each cavity in a multi-cavity injection mold is identical. This requires that cavity dimensions should be identical and delivery system of melt to each cavity have to be the same. Despite the geometrically balanced layout in multi-cavity injection mold more than 4 cavities, it has been observed that the filling in each cavity results in imbalances. Most of cases, this phenomenon of filling imbalances have a bad effect on dimension accuracy, warpage, molding appearance and strength of molding parts. In this study, experiment were conducted to investigate the effect of filling imbalances on the molding quality(surface gloss, shrinkage, tensile strength) in the multy-cavity injection mold.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.5 s.347
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• pp.54-63
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• 2006

This work proposes a 14b 100MS/s 0.18um CMOS ADC with optimized resolution, conversion speed, die area, and power dissipation to obtain the performance required in the fourth-generation mobile communication systems. The 3-stage pipeline ADC, whose optimized architecture is analyzed and verified with behavioral model simulations, employs a wide-band low-noise SHA to achieve a 14b level ENOB at the Nyquist input frequency, 3-D fully symmetric layout techniques to minimize capacitor mismatch in two MDACs, and a back-end 6b flash ADC based on open-loop offset sampling and interpolation to obtain 6b accuracy and small chip area at 100MS/s. The prototype ADC implemented in a 0.18um CMOS process shows the measured DNL and INL of maximum 1.03LSB and 5.47LSB, respectively. The ADC demonstrates a maximum SNDR and SFDR of 59dB and 72dB, respectively, and a power consumption of 145mW at 100MS/s and 1.8V. The occupied active die area is $3.4mm^2$.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.3
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• pp.82-88
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• 2015

This paper presents a design of the enable switch circuit, which is consist of discrete device at smart junction box(SJB) board. The Enable switch circuit, which receives ignition signal (IG) for input, sends a drive signal to linear regulator and other elements. The circuit design is carried out in a BCDMOS $0.18{\mu}m$ technology, and the performances are verified through simulations according to AEC-Q100 and ISO 7637-2. Die area of the designed Enable switch circuit is $1.67mm{\times}0.54mm$ in layout, and it is shown that the die can be housed in $3mm{\times}3mm$ HVSON8 package. The designed enable switch circuit is expected to be widely adopted in various automotive SJB's since it can significantly reduce the overall printed circuit board form factor.