• 한국IT서비스학회지
• /
• 제11권sup호
• /
• pp.51-60
• /
• 2012

In this paper, we provide the analysis of device model and method between device models for compatible M&S V&V of the NetSPIN. First of all, we analysis features, structure, and classification of the NetSPIN. The second, as a part of reliable V&V process, we analysis network system modeling process, correlation between device modeling process for M&S of the NetSPIN. The third, we suggest making a kind of pool of reference model and module of devices for the increase factor of reuse between device model. We also, at the point view of M&S V&V, conclude that there is the validity of the fidelity in device modeling process. Through the analysis of the NetSPIN device model and suggestion of the method for higher compatibility between device modes, the development process of device model be clearly understood. Also we present the effective method of the development for reliable device mode as the point of V&V.

• 한국전기전자재료학회:학술대회논문집
• /
• 한국전기전자재료학회 1998년도 추계학술대회 논문집
• /
• pp.49-52
• /
• 1998

In this paper, to implement the electrical equivalent modeling of powder electroluminescent device, capacitate equation of device was chosen. The conventional structure device which have dielectric and phosphor layer between electrodes, and the single emission structure device which means that dielectric and phosphor were mixed between electrodes, were investigated. As a result, it was possible to make the equation that is transferred capacitance to phosphor layer, and using measured brightness efficiency and conductivity of devices was calculated.

• 한국항행학회논문지
• /
• 제24권4호
• /
• pp.314-321
• /
• 2020

LASAR (logic automated stimulus and response) 소프트웨어는 디지털 전자 회로 카드에 대한 로직 기능시험 및 고장검출을 위한 자동점검프로그램 개발도구이다. LASAR 소프트웨어는 소자의 논리회로 기능 및 입·출력 정의된 정보가 필요하다. 소자 정보가 없으면 정상적인 부품 모델링이 불가능하다. 따라서 본 논문에서는 소자 정보가 없는 PLD (programmable logic device) 소자를 역설계 방법을 통하여 부품 모델링을 수행한다. 개발된 LASAR 프로그램은 고장 시뮬레이션 결과와 단일 고착 고장삽입 방법을 통해 고장 검출율을 확인하였다. 고장 검출율은 기존의 제한적인 모델링은 91%, 역설계를 통한 모델링은 94%로 3% 상승하였다. 또한, EP 310 PLD 소자에 대한 입·출력핀에 대한 22가지 고착결함의 경우 100% 검출하여 양호한 성능을 확인하였다.

• 한국광학회지
• /
• 제14권3호
• /
• pp.306-311
• /
• 2003

본 논문에서는 광전송시스템에서 파장분할다중화 광소자로 사용되는 박막필터형 광소자의 특성 분석 및 평가를 위해 입력광원을 모델링 하였으며 광경로에 대해 광선추적법을 사용하여 전산모의 한 광특성을 실험과 비교, 분석하였다. 그 결과 입력광원에 대한 cell 방식의 모델링이 결합효율의 정확도 및 가우시안 강도분포에 접근성을 볼 때 마이크로 옵틱스형 광소자 분석함에 있어 적합함을 알 수 있다. 박막필터형 광소자에 대한 최적 전산모의 결과 광섬유와 GRIN 렌즈 사이 거리가 0.24mm이며 GRIN 렌즈와 박막필터 사이 거리가 0.25mm일 때 최대 결합효율은 -0.11 ㏈이었으며 동일한 조건에의 실험결과 -0.35 ㏈의 최대 결합효율을 얻었다. 이것은 단심 및 이심페룰, GRIN 렌즈 등과 같은 구성품의 불완전성과 박막필터에 의한 손실을 고려할 때, 전산모의 결과와 매우 일치하는 것으로서 본 연구에서 제안한 입력광원의 모델링을 적용한 전산모의가 박막필터형 광소자의 특성을 예측할 수 있음을 보였다.

• 한국전기전자재료학회논문지
• /
• 제14권3호
• /
• pp.241-245
• /
• 2001

In this paper, we present parameter optimization technique for GaAs/AlGaAs multiple quantum well avalanche photodiodes used for image capture mechanism in high-definition system. Even under flawless environment in semiconductor manufacturing process, random variation in process parameters can bring the fluctuation to device performance. The precise modeling for this variation is thus required for accurate prediction of device performance. The precise modeling for this variation is thus required for accurate prediction of device performance. This paper will first use experimental design and neural networks to model the nonlinear relationship between device process parameters and device performance parameters. The derived model was then put into genetic algorithms to acquire optimized device process parameters. From the optimized technique, we can predict device performance before high-volume manufacturign, and also increase production efficiency.

• 대한전자공학회:학술대회논문집
• /
• 대한전자공학회 2004년도 학술대회지
• /
• pp.780-783
• /
• 2004

The two-dimensional modeling of the non-stationary thermal state and voltage responsivity of the sensitive elements usually used in solid-state pyroelectric focal plane arrays are presented. Temperature distributions under periodical thermal excitation and the response of the thermal imaging device, which is composed of the pyroelectric sensitive elements mounted on a single silicon substrate, are numerically calculated. The sensitive element consists of a covering metal layer, infrared polymer absorber, front metal contact, sensitive pyroelectric element, the interconnecting column and the bulk silicon readout. The results of the numerical modeling show that the thermal crosstalk between sensitive elements to be critical especially at low frequency (f < 10Hz) of periodically modulated light. It is also shown that the use of our models gives the possibility to improve the design, operating regimes and sensitivity of the device.

• 한국CDE학회논문집
• /
• 제19권2호
• /
• pp.191-201
• /
• 2014

A 3D CAD system that can be used on a smart device is proposed. Smart devices are now a part of everyday life and also are widely being used in various industry domains. The proposed 3D CAD system would allow modeling in a rapid and intuitive manner on a smart device when an engineer makes a 3D model of a product while moving in an engineering site. There are several obstacles to develop a 3D CAD system on a smart device such as low computing power and the small screen of smart devices, imprecise touch inputs, and transfer problems of created 3D models between PCs and smart devices. The author discusses the system design of a 3D CAD system on a smart device. The selection of the modeling operations, the assignment of touch gestures to these operations, and the construction of a geometric kernel for creating both meshes and a procedural CAD model are introduced. The proposed CAD system has been implemented for validation by user tests and to demonstrate case studies using test examples. Using the proposed system, it is possible to produce a 3D editable model swiftly and simply in a smart device environment to reduce design time of engineers.

• JSTS:Journal of Semiconductor Technology and Science
• /
• 제13권4호
• /
• pp.342-354
• /
• 2013

The aim of this work is to investigate and study the quantum effects in the modeling of nanoscale symmetric double-gate InAlAs/InGaAs/InP HEMT (High Electron Mobility Transistor). In order to do so, the carrier concentration in InGaAs channel at gate lengths ($L_g$) 100 nm and 50 nm, are modelled by a density gradient model or quantum moments model. The simulated results obtained from the quantum moments model are compared with the available experimental results to show the accuracy and also with a semi-classical model to show the need for quantum modeling. Quantum modeling shows major variation in electron concentration profiles and affects the device characteristics. The two triangular quantum wells predicted by the semi-classical model seem to vanish in the quantum model as bulk inversion takes place. The quantum effects thus become essential to incorporate in nanoscale heterostructure device modeling.

• 반도체디스플레이기술학회지
• /
• 제5권4호
• /
• pp.29-34
• /
• 2006

In order to design an OLED(Organic Luminescent Emitting Device) evaporation system, geometric simulation of film thickness distribution profile is required. For the OLED evaporation process, thin film thickness uniformity is of great practical importance. In this paper, a geometric modeling algorithm is introduced for process simulation of the OLED evaporating process. The physical fact of the evaporating process is modeled mathematically. Based on the developed method, the thickness of the thin-film layer can be successfully controlled.

• ETRI Journal
• /
• 제27권5호
• /
• pp.628-634
• /
• 2005

From AC analysis results utilizing a 2-dimensional device simulator, we extracted an AC-equivalent circuit of a grounded-gate NMOS (ggNMOS) electrostatic discharge (ESD) protection device. The extracted equivalent circuit is utilized to analyze the effects of the parasitics in a ggNMOS protection device on the characteristics of a low noise amplifier (LNA). We have shown that the effects of the parasitics can appear exaggerated for an impedance matching aspect and that the noise contribution of the parasitic resistances cannot be counted if the ggNMOS protection device is modeled by a single capacitor, as in prior publications. We have confirmed that the major changes in the characteristics of an LNA when connecting an NMOS protection device at the input are reduction of the power gain and degradation of the noise performance. We have also shown that the performance degradation worsens as the substrate resistance is reduced, which could not be detected if a single capacitor model is used.