• JSTS:Journal of Semiconductor Technology and Science
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• v.8 no.3
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• pp.251-263
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• 2008

In this paper, we report an analytical modeling and 2-D Synopsys Sentaurus TCAD simulation of ion implanted silicon carbide MESFETs. The model has been developed to obtain the threshold voltage, drain-source current, intrinsic parameters such as, gate capacitance, drain-source resistance and transconductance considering different fabrication parameters such as ion dose, ion energy, ion range and annealing effect parameters. The model is useful in determining the ion implantation fabrication parameters from the optimization of the active implanted channel thickness for different ion doses resulting in the desired pinch off voltage needed for high drain current and high breakdown voltage. The drain current of approximately 10 A obtained from the analytical model agrees well with that of the Synopsys Sentaurus TCAD simulation and the breakdown voltage approximately 85 V obtained from the TCAD simulation agrees well with published experimental results. The gate-to-source capacitance and gate-to-drain capacitance, drain-source resistance and trans-conductance were studied to understand the device frequency response. Cut off and maximum frequencies of approximately 10 GHz and 29 GHz respectively were obtained from Sentaurus TCAD and verified by the Smith's chart.

• Journal of the Korean Society for Precision Engineering
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• v.24 no.8 s.197
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• pp.138-143
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• 2007

Microstereolithography technology is similar to the conventional stereolithography process and enables to fabricate a complex 3D microstructure. This is divided into scanning and projection type according to aiming at precision and fabrication speed. The scanning MSL fabricates each layer using position control of laser spot on the resin surface, whereas the projection MSL fabricates one layer with one exposure using a mask. In the projection MSL, DMD used to generate dynamic pattern consists of $1024{\times}768$ micromirrors which have $13.68{\mu}m$ per side. The fabrication range and resolution are determined by the field of view of the DMD and the magnification of the projection lens. If using the projection lens with high power, very fine microstructures can be fabricated. In this paper, the projection MSL system adapted to a large surface for array-type fabrication is presented. This system covers the meso range, which is defined as the intermediate range between micro and macro, with a resolution of a few ${\mu}m$. The fabrication of array-type microstructures has been demonstrated to verify the performance of implemented system.

• Current Optics and Photonics
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• v.4 no.6
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• pp.509-515
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• 2020

A practical single photon source for fiber-based quantum information processing is still lacking. As a possible 1.55-㎛ quantum-dot single photon source, an InGaAsP/InP-air-aperture micropillar cavity is investigated in terms of fabrication tolerance. By properly modeling the processing uncertainty in layer thickness, layer diameter, surface roughness and the cavity shape distortion, the fabrication imperfection effects on the cavity quality are simulated using a finite-difference time-domain method. It turns out that, the cavity quality is not significantly changing with the processing precision, indicating the robustness against the imperfection of the fabrication processing. Under thickness error of ±2 nm, diameter uncertainty of ±2%, surface roughness of ±2.5 nm, and sidewall inclination of 0.5°, which are all readily available in current material and device fabrication techniques, the cavity quality remains good enough to form highly efficient and coherent 1.55-㎛ single photon sources. It is thus implied that a quantum dot contained InGaAsP/InP-air-aperture micropillar cavity is prospectively a practical candidate for single photon sources applied in a fiber-based quantum information network.

• Journal of Photoscience
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• v.10 no.3
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• pp.251-255
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• 2003

The composites fabricated by blending nonlinear optical (NLO) chromophore such as {4-[2-(4-nitrophenyl)-vinyl] phenyl}diphenylamine (NVPDA) with photoconducting crosslinkable matrix, bis-(4-ethynylphenyl)-(4-octyloxy-phenyl)amine (BEOPEA), showed photorefractive property. Many problems faced in typical organic photorefractive systems such as time-consuming chemical synthesis, difficulty in rational design, intrinsic instability and phase separation could be avoided by this fabrication method.

• Proceedings of the Polymer Society of Korea Conference
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• 2006.10a
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• pp.13-14
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• 2006

The use of soft-lithography instead of standard photolithography and dry etching technologies is attractive because inexpensive optical device can be realized. Polymerization using multi-photon absorption of materials is also a good method for optical waveguide fabrication. Laser induced self-writing technology of optical waveguide is also very simple and attractive. Using these processes, we can fabricate and interconnect optical circuits at once. In this presentation, several simple fabrication methods will be introduced. New optical loss evaluation method for polymer optical waveguides will also be presented

• 한국정보디스플레이학회:학술대회논문집
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• 2008.10a
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• pp.222-225
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• 2008

We proposed the dry etching process recipe for the fabrication of In-Ga-Zn-O (IGZO)-based oxide TFTs, in which the etching behaviors of IGZO films were systematically investigated when the etching gas mixtures and their mixing ratios were varied. Good device characteristics of the fabricated TFT were successfully confirmed.

• Applied Science and Convergence Technology
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• v.23 no.5
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• pp.284-288
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• 2014

We present tapered nanostructures fabricated on a selective area of gallium phosphide substrates for advanced optoelectronic device applications. A lithography-free fabrication process was accomplished by dry etching of metal nanoparticles. Thermal dewetting of micro-patterned metal thin films provides etch masks for tapered nanostructures. This simple process also allows the formation of plasmonic surfaces with corrugated shapes. Rigorous coupled-wave analysis calculations provide design guidelines for tapered nanostructures on gallium phosphide substrates.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.06a
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• pp.440-440
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• 2009

Semiconductor nanowires offer exciting possibilities as components of solar cells and have already found applications as active elements in organic, dye-sensitized, quantum-dot sensitized, liquid-junction, and inorganic solid-state devices. Among many semiconductors, silicon is by far the dominant material used for worldwide photovoltaic energy conversion and solar cell manufacture. For silicon wire to be used for solar device, well aligned wire arrays need to be fabricated vertically or horizontally. Macroscopic silicon wire arrays suitable for photovoltaic applications have been commonly grown by the vapor-liquid-solid (VLS) process using metal catalysts such as Au, Ni, Pt, Cu. In the case, the impurity issues inside wire originated from metal catalyst are inevitable, leading to lowering the efficiency of solar cell. To escape from the problem, the wires of purity of wafer are the best for high efficiency of photovoltaic device. The fabrication of wire arrays by the electrochemical etching of silicon wafer with photolithography can solve the contamination of metal catalyst. In this presentation, we introduce silicon wire arrays by electrochemical etching method and then fabrication methods of radial p-n junction wire array solar cell and the various merits compared with conventional silicon solar cells.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2000.04b
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• pp.14-17
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• 2000

The rise throughput and the stability in fabrication of device can be obtained by applying of CMP process to STI structure in 0.18um semiconductor device. To employ in STI CMP, the reverse moat process has been added thus the process became complex and the defects were seriously increased. Removal rates of each thin films in STi CMP was not equal hence the devices must to be effected, that is, the damage was occured in the device dimension in the case of excessive CMP process and the nitride film was remained on the device dimension in the case of insufficient CMP process than these defects affect the device characteristics. We studied the current sensing method in STI-CMP with the reverse moat pattern.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2001.07a
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• pp.33-36
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• 2001

Chemical mechanical polishing(CMP) process has been widely used to planarize dielectric layers, which can be applied to the integrated circuits for deep sub-micron technology. The rise throughput and the stability in the device fabrication can be obtained by applying of CMP process to STI structure in 0.18$\mu\textrm{m}$ m semiconductor device. The reverse moat process has been added to employ in of each thin films in STI-CMP was not equal, hence the devices must to be effected, that is, the damage was occurred in the device area for the case of excessive CMP process and the nitride film was remained on the device area for the case of insufficient CMP process, and than, these defects affect the device characteristics. Also, we studied the High Selectivity Slurry(HSS) to perform global planarization without reverse moat step.