• Title/Summary/Keyword: Detection circuit

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Vision chip for edge detection with a function of pixel FPN reduction (픽셀의 고정 패턴 잡음을 감소시킨 윤곽 검출용 시각칩)

  • Suh, Sung-Ho;Kim, Jung-Hwan;Kong, Jae-Sung;Shin, Jang-Kyoo
    • Journal of Sensor Science and Technology
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    • v.14 no.3
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    • pp.191-197
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    • 2005
  • When fabricating a vision chip, we should consider the noise problem, such as the fixed pattern noise(FPN) due to the process variation. In this paper, we propose an edge-detection circuit based on biological retina using the offset-free column readout circuit to reduce the FPN occurring in the photo-detector. The offset-free column readout circuit consists of one source follower, one capacitor and five transmission gates. As a result, it is simpler and smaller than a general correlated double sampling(CDS) circuit. A vision chip for edge detection has been designed and fabricated using $0.35\;{\mu}m$ 2-poly 4-metal CMOS technology, and its output characteristics have been investigated.

A Process Detection Circuit using Self-biased Super MOS composit Circuit (자기-바이어스 슈퍼 MOS 복합회로를 이용한 공정 검출회로)

  • Suh Benjamin;Cho Hyun-Mook
    • Journal of the Institute of Convergence Signal Processing
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    • v.7 no.2
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    • pp.81-86
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    • 2006
  • In this paper, a new process detection circuit is proposed. The proposed process detection circuit compares a long channel MOS transistor (L > 0.4um) to a short channel MOS transistor which uses lowest feature size of the process. The circuit generates the differential current proportional to the deviation of carrier mobilities according to the process variation. This method keep the two transistor's drain voltage same by implementing the feedback using a high gain OPAMP. This paper also shows the new design of the simple high gam self-biased rail-to-rail OPAMP using a proposed self-biased super MOS composite circuit. The gain of designed OPAMP is measured over 100dB with $0.2{\sim}1.6V$ wide range CMR in single stage. Finally, the proposed process detection circuit is applied to a differential VCO and the VCO showed that the proposed process detection circuit compensates the process corners successfully and ensures the wide rage operation.

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Miniaturized Sensor Interface Circuit for Respiration Detection System (호흡 검출 시스템을 위한 초소형 센서 인터페이스 회로)

  • Jo, Sung-Hun
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.25 no.8
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    • pp.1130-1133
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    • 2021
  • In this paper, a miniaturized sensor interface circuit for the respiration detection system is proposed. Respiratory diagnosis is one of the main ways to predict various diseases. The proposed system consists of respiration detection sensor, temperature sensor, and interface circuits. Electrochemical type gas sensor using solid electrolytes is adopted for respiration detection. Proposed system performs sensing, amplification, analog-to-digital conversion, digital signal processing, and i2c communication. And also proposed system has a small form factor and low-cost characteristics through optimization and miniaturization of the circuit structure. Moreover, technique for sensor degradation compensation is introduced to obtain high accuracy. The size of proposed system is about 1.36 cm2.

The defect detection circuit of an electronic circuit through impedance change detection that induces a change in S-parameter (S-parameter의 변화를 유도하는 임피던스 변화 감지를 통한 전자회로의 결함검출회로)

  • Seo, Donghwan;Kang, Tae-yeob;Yoo, Jinho;Min, Joonki;Park, Changkun
    • Journal of IKEEE
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    • v.25 no.4
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    • pp.689-696
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    • 2021
  • In this paper, in order to apply Prognostics and Health Management(PHM) to an electronic system or circuit, a circuit capable of detecting and predicting defect characteristics inside the system or circuit is implemented, and the results are described. In the previous study, we demonstrated that the frequency of the amplitude of S-parameter changed as the circuit defect progressed. These characteristics were measured by network analyser. but in this study, even if the same defect detection method is used, a circuit is proposed to check the progress of the defect, the remaining time, and the occurrence of the defect without large measurement devices. The circuit is designed to detect the change in impedance that generates changes of S-parameter, and it is verified through simulation using the measurement results of Bond-wires.

A Novel Fault Detection Method using the PWM Characteristic at Open-Circuit Fault in NPC Inverter Systems (NPC 인버터 시스템에서 개방성 고장시 PWM 특성을 이용한 새로운 고장 검출 방법)

  • Lee, Jung-Dae;Kim, Tae-Jin;Ha, Dong-Hyun;Hyun, Dong-Seok
    • The Transactions of The Korean Institute of Electrical Engineers
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    • v.57 no.7
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    • pp.1200-1207
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    • 2008
  • In this paper, a novel fault detection method is proposed when the neutral-point-clamped inverter has a open-circuit fault in the switching device. This proposed method is configured with simple circuit and is achieved by a simple algorithm using the inherent characteristic of the continuous Pulse Width Modulation. Also, this method has the fast fault detection ability and is much simpler to embody, in comparison with conventional fault detection methods. This ability to detect fault minimizes harmful effect which are such as DC-link voltage unbalance and overstress to other switching devices. Therefore, this proposed fault detection method can improve reliability of NPC inverter system. Experimental results are presented to verify the validity of proposed fault detection method.

A Study on Fault Detection and Fault Device Estimation Method for Cab Cubicle in High Speed Electrical Train (고속전철용 Cab Cubicle의 이상검출과 고장부위 추정에 관한 연구)

  • 장영건;조경환;박계서;최권희
    • Proceedings of the KSR Conference
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    • 2000.05a
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    • pp.188-194
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    • 2000
  • This study is about fault detection and fault area detection of LV circuit in Cab Cubicle system which have control of train to keep safety in High Speed Train. LV circuit is operated with diagnosis system like safety system. In this paper, we suggest a design and an implementation method to detect fault or to detect fault area automatically about LV circuit. The implemented system is tested successfully after implementation of some function. We expect reduction to diagnosis area or repair time by fault area module

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A Study of the Current Reference Signal Generation Circuit for Single-Phase Harmonic Elimination Systems (단상 전원 고조파 제거 시스템을 위한 기준전류 생성회로에 대한 연구)

  • Jung Done-youl;Park Chong-yeon;Kim Sang-hun;Choi Won-ho
    • The Transactions of the Korean Institute of Electrical Engineers B
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    • v.54 no.7
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    • pp.335-342
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    • 2005
  • This paper presents a circuit to generate the current reference signal for single-phase harmonic elemination systems. Some of conventional methods for the current reference signal generation based on neural network algorithms. It requires complex circuitry to implement. the simplest method is to use analog filters. but it is difficult to obtain good current reference signals. So, we propose the harmonic detection circuit using GIC(Generalized Impedance Converter) for the purpose of low cost ,simple circuitry and high performance, Simulation and experimental results verify that the proposed circuit has better harmonic detection performance than conventional circuit.

Detection of Stator Winding Inter-Turn Short Circuit Faults in Permanent Magnet Synchronous Motors and Automatic Classification of Fault Severity via a Pattern Recognition System

  • CIRA, Ferhat;ARKAN, Muslum;GUMUS, Bilal
    • Journal of Electrical Engineering and Technology
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    • v.11 no.2
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    • pp.416-424
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    • 2016
  • In this study, automatic detection of stator winding inter-turn short circuit fault (SWISCFs) in surface-mounted permanent magnet synchronous motors (SPMSMs) and automatic classification of fault severity via a pattern recognition system (PRS) are presented. In the case of a stator short circuit fault, performance losses become an important issue for SPMSMs. To detect stator winding short circuit faults automatically and to estimate the severity of the fault, an artificial neural network (ANN)-based PRS was used. It was found that the amplitude of the third harmonic of the current was the most distinctive characteristic for detecting the short circuit fault ratio of the SPMSM. To validate the proposed method, both simulation results and experimental results are presented.

A light-adaptive CMOS vision chip for edge detection using saturating resistive network (포화 저항망을 이용한 광적응 윤곽 검출용 시각칩)

  • Kong, Jae-Sung;Suh, Sung-Ho;Kim, Jung-Hwan;Shin, Jang-Kyoo;Lee, Min-Ho
    • Journal of Sensor Science and Technology
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    • v.14 no.6
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    • pp.430-437
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    • 2005
  • In this paper, we proposed a biologically inspired light-adaptive edge detection circuit based on the human retina. A saturating resistive network was suggested for light adaptation and simulated by using HSPICE. The light adaptation mechanism of the edge detection circuit was quantitatively analyzed by using a simple model of the saturating resistive element. A light-adaptive capability of the edge detection circuit was confirmed by using the one-dimensional array of the 128 pixels with various levels of input light intensity. Experimental data of the saturating resistive element was compared with the simulated results. The entire capability of the edge detection circuit, implemented with the saturating resistive network, was investigated through the two-dimensional array of the $64{\times}64$ pixels

FPGA-based Implementation of Fast Edge Detection using Sobel Operator (소벨 연산을 이용한 FPGA 기반 고속 윤곽선 검출 회로 구현)

  • Ryu, Sang-Moon
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.26 no.8
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    • pp.1142-1147
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    • 2022
  • The edges of image should be detected first so that the objects in the image can be identified. An hardware-implemented edge detection algorithm outperforms its software version. Sobel operation is the most suitable algorithm for an hardware implementation of edge detection. And lots of works have been done to perform Sobel operations efficiently on FPGA-based hardware. This work proposes how to implement fast edge detection circuit on FPGA, which is based on the conventional circuit for edge detection using Sobel operator. The newly proposed circuit is suitable for processing images when the images are stored in memory devices and outperforms the conventional one with little additional FPGA resources. Both the conventional circuit and the proposed circuit were implemented on an FPGA. And the result showed that the proposed circuit almost doubles the performance in processing images and needs little additional FPGA resources.