• Communications for Statistical Applications and Methods
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• v.12 no.1
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• pp.181-189
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• 2005

This paper suggest a method of inclusion probability proportional to size sampling that provides a non-negative and stable variance estimator. The sampling procedure is quite simple and flexible since a sampling design is easily obtained using mathematical programming. This scheme appears to be preferable to Nigam, Kumar and Gupta's (1984) method which uses a balanced incomplete block designs. A comparison is made with their method through an example in the literature.

• Transactions of the Korean Society of Automotive Engineers
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• v.13 no.4
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• pp.39-48
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• 2005

Finite element analyses have been performed for the purpose of obtaining the robust and reliable design of engine cylinder block. Fatigue under high cycle operating loads is a primary concern and is evaluated by a probabilistic method. The robust and reliable design by a probabilistic method can provide satisfactory design conditions for the performance of the system under the influence of noise factors. Therefore, the design by this method will be desensitized to the uncontrollable noise factors. The simple methodology evaluates the distortion of main bore is proposed for the purpose of maintaining a well-controlled clearance between the crankshaft and main bores. The proposed methodology has proven a capability of predicting the distortion of the main bore under assembly, thermal, and firing loads. The calculated results are correlated well with the experimental ones.

• Transactions of the Korean Society of Automotive Engineers
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• v.6 no.5
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• pp.211-221
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• 1998

Thermal behavior on the cylinder block of a 4-cylinder, 4-stroke 2.0L SOHC gasoline engine was numerically and experimentally analyzed. The numerical calculation was performed using the finite element method. The cylinder block was modelled as a three dimensional finite element by considering its geometry. The physical domain was devided into hexahedron elements. 16 thermocouples were installed at points of 2mm inside from cylinder wall near top ring of piston in cylinder block, which points have suffered major thermal loads and suggested as proper measurement points for engine design by industrial engineers. Under full load and 9$0^{\circ}C$ coolant temperature condition, temperature behavior of cylinder block according to engine speed were analyzed. The results showed that temperature rose gradually to conform to a function of 2nd~4th order of engine speed at intake side, exhaust and siamese side, respectively. As engine load was changed from 100 to 50% by 25% step, temperature curve also conformed to 2nd~7th order function of engine speed. Temperature differences by load condition were similar among 100, 75% and 50%. Under full load and coolant temperature of 11$0^{\circ}C$, temperature behavior were also analyzed and the result also showed conformance to 2n d~7th order function of engine speed. Temperature curve was transferred in parallel upwards corresponding coolant temperature rise.

• 한국데이터정보과학회:학술대회논문집
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• 2006.04a
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• pp.121-129
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• 2006

Two color or cDNA microarrays are extensively used to study relative expression levels of thousands of genes simultaneously. 0かy two tissue samples can be hybridized on a single microarray slide. Thus, a microarray slide necessarily forms an incomplete block design with block size two when more than two tissue samples are under study. We also need to control for variability in gene expression values due to the two dyes. Thus, red and green dyes form the second blocking factor in addition to slides. General design problem for these microarray experiments is discussed in this paper. Designs for factorial cDNA microarrays are also discussed.

• ETRI Journal
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• v.34 no.1
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• pp.44-54
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• 2012

Because of the intrinsic lack of internal-system observability and controllability in highly integrated multicore processors, very restricted access is allowed for the debugging of erroneous chip behavior. Therefore, the building of an efficient debug function is an important consideration in the design of multicore processors. In this paper, we propose a flexible on-chip debug architecture that embeds a special logic supporting the debug functionality in the multicore processor. It is designed to support run-stop-type debug functions that can halt and control the execution of the multicore processor at breakpoint events and inspect the possible causes of any errors. The debug architecture consists of the following three functional components: the core debug support block, the multicore debug support block, and the debug interface and control block. By embedding this debug infrastructure, the embedded processor cores within the multicore processor can be debugged simultaneously as well as independently. The debug control is performed by employing a JTAG-based scanning operation. We apply this on-chip debug architecture to build a debugger for a prototype multicore processor and demonstrate the validity and scalability of our approach.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.12 no.2
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• pp.53-64
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• 2002

This paper describes a design of cryptographic processor that implements the AES (Advanced Encryption Standard) block cipher algorithm, "Rijndael". An iterative looping architecture using a single round block is adopted to minimize the hardware required. To achieve high throughput rate, a sub-pipeline stage is added by dividing the round function into two blocks, resulting that the second half of current round function and the first half of next round function are being simultaneously operated. The round block is implemented using 32-bit data path, so each sub-pipeline stage is executed for four clock cycles. The S-box, which is the dominant element of the round block in terms of required hardware resources, is designed using arithmetic circuit computing multiplicative inverse in GF($2^8$) rather than look-up table method, so that encryption and decryption can share the S-boxes. The round keys are generated by on-the-fly key scheduler. The crypto-processor designed in Verilog-HDL and synthesized using 0.25-$\mu\textrm{m}$ CMOS cell library consists of about 23,000 gates. Simulation results show that the critical path delay is about 8-ns and it can operate up to 120-MHz clock Sequency at 2.5-V supply. The designed core was verified using Xilinx FPGA board and test system.

• Journal of the Korean housing association
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• v.20 no.6
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• pp.111-118
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• 2009

In modern Asia major cities had same problem with lack of affordable housing for families. So they had to concentrate to the mass supply of housing and made some physical counter effects like high density of cities, limitation of parking space. Also people who lived in those cities could suffer from broken traditional community culture. To rebuild traditional community and increase land usage, Block housing is suggested as a new kind of multi-family housing for old town redevelopment. Now some governments are trying to make urban code to give some initiative for new block housing development in old city blocks. They expect this new housing type can help to solve serious problems like lack of parking area, green space and context of block. Also they hope that block housing development can help to increase safety of town and reduce cost of development. The purpose of this study is to review the establishment and development process of Block Housing and to confirm the aspect which has been changed with urban organization together. Also this study tried to find out the intentional characteristics of similarities and differences with comparison of Korea and Japan. And as a result we could find critical physical viewpoint, and provide considerations for future study and plan. Several cases of block housing in Korea and Japan were reviewed for comparative study and Post Occupancy Evaluation (POE) survey was examined to find satisfaction factors and problems which were expected to improved.

• Journal of The Korea Institute of Healthcare Architecture
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• v.19 no.2
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• pp.51-59
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• 2013

Purpose: At the moment, a lot of poor older people live in permanent rental housing in Korea. But many rental apartments are not suitable for elderly living because most of them have many problems related to the lack of accessibility and adaptability for older people with physical and mental disabilities. So it is necessary to upgrade the old permanent rental housing for convenience of elderly living. The purpose of this paper is to construct basic data for remodeling of worn out and small rental housing block in order to realize the concept of "Aging in Place". Methods: Questionnaires and interviews about elderly living have been conducted on 104 elderly who live in Suwon Wooman permanent rental apartment block which was constructed 21 years ago. From the collected data, dining pattern, inconvenient area, small area, satisfaction level on unit area and demand for unit expansion type have been analysed in order to find out the direction for remodeling of permanent rental apartment unit. Results: The problems of existing permanent rental apartment can be summarized into improper laundry space, small dining area, inconvenient bath and so on. According to the family size, the elderly resident has the different preference about the expansion type of his resident unit. Big families usually want to enlarge their living unit though they pay for additional monthly rental fee. Implications: Lifetime home concept adopting Universal Design has to be applied to the whole residential block especially to the social rental housing. And this concept had better be expanded to Lifetime neighbor design.

• Proceedings of the IEEK Conference
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• 1999.06a
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• pp.403-406
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• 1999

Among the compression methods of moving picture information, a motion estimation method is used to remove time-repeating. The Block Matching Algorithm in motion estimation methods is the commonest one. In recent days, it is required the more advanced high quality in many image processing fields, for example HDTV, etc. Therefore, we have to accomplish not by means of Partial Search Algorithm, but by means of Full Search Algorithm in Block Matching Algorithm. In this paper, it is suggested a structure that reduce total calculation quantity and size, because the structure using Bit Plane select and use only 3bit of 8bit luminance signal.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.12 no.3
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• pp.432-438
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• 2001

In this paper, after applying Defected Ground Structure(DGS) to DC block, changes of gap and length of λ/4 coupled line are investigated by EM simulation and fabrication. As a result, on condition of the same output with the case using typical DC block, the gap between λ/4 coupled line is widen from 0.1 mm to 0.46 mm by 0.36 mm and the length of λ/4 coupled line gets shorter from 17.7 mm to 13.2 mm by 4.5 mm. Also three type power amplifiers using blocking capacitor, typical DC block and DGS DC block are fabricated and investigated. At first, when S parameter characteristics of each amplifier are considered at frequency band of 3.2 +-0.O5 GHz, every amplifier has similar characteristics of gain and S parameter. Second when the output power of amplifiers is 25 dBm after putting CW signal of 3.2 GHz into three type amplifiers, the difference of dominant signal and 2nd harmonic signal using blocking capacitor, typical DC block and DGS DC block is each -44.83 dBc, -66.84 dBc and -64.33 dBc. Therefore harmonic characteristics of amplifiers using typical DC block and DGS DC block is almost same.