• Korean Journal of Computational Design and Engineering
• /
• v.12 no.4
• /
• pp.245-254
• /
• 2007

This research proposed feature extraction algorithms as an input of STEP Ap214 data, and feature parameterization process to simplify further design change and maintenance. The procedure starts with suppression of blend faces of an input solid model to generate its simplified model, where both constant and variable-radius blends are considered. Most existing cell decomposition algorithms utilize concave edges, and they usually require complex procedures and computing time in recomposing the cells. The proposed algorithm using reference features, however, was found to be more efficient through testing with a few sample cases. In addition, the algorithm is able to recognize depression features, which is another strong point compared to the existing cell decomposition approaches. The proposed algorithm was implemented on a commercial CAD system and tested with selected industrial product models, along with parameterization of recognized features for further design change.

• Proceedings of the IEEK Conference
• /
• 2003.07e
• /
• pp.2355-2358
• /
• 2003

The purpose of this paper is to investigate two major feature extraction techniques based on generic modular face recognition system. Detailed algorithms are described for principal component analysis (PCA) and independent component analysis (ICA). PCA and ICA ate statistical techniques for feature extraction and their incorporation into a face recognition system requires numerous design decisions. We explicitly state the design decisions by introducing a modular-based face recognition system since some of these decision are not documented in the literature. We explored different implementations of each module, and evaluate the statistical feature extraction algorithms based on the FERET performance evaluation protocol (the de facto standard method for evaluating face recognition algorithms). In this paper, we perform two experiments. In the first experiment, we report performance results on the FERET database based on PCA. In the second experiment, we examine performance variations based on ICA feature extraction algorithm. The experimental results are reported using four different categories of image sets including front, lighting, and duplicate images.

• Journal of the Institute of Electronics Engineers of Korea SP
• /
• v.43 no.2 s.308
• /
• pp.82-86
• /
• 2006

The design of a pattern recognition system generally involves the three aspects: preprocessing, feature extraction, and decision making. Among them, a feature extraction method determines an appropriate subspace of dimensionality in the original feature space of dimensionality so that it can reduce the complexity of the system and help to improve successful recognition rates. Linear transforms, such as principal component analysis, factor analysis, and linear discriminant analysis have been widely used in pattern recognition for feature extraction. This paper shows that singular value decomposition (SVD) can be applied usefully in feature extraction stage of pattern recognition. As an application, a remote sensing problem is applied to verify the usefulness of SVD. The experimental result indicates that the feature extraction using SVD can improve the recognition rate about 25% compared with that of PCA.

• Journal of IKEEE
• /
• v.17 no.3
• /
• pp.241-247
• /
• 2013

This paper presents the design of a System on Programmable Chip (SoPC) based on Field Programmable Gate Array (FPGA) for speech recognition in which Mel-Frequency Cepstral Coefficients (MFCC) for speech feature extraction and Vector Quantization for recognition are used. The implementing process of the speech recognition system undergoes the following steps: feature extraction, training codebook, recognition. In the first step of feature extraction, the input voice data will be transformed into spectral components and extracted to get the main features by using MFCC algorithm. In the recognition step, the obtained spectral features from the first step will be processed and compared with the trained components. The Vector Quantization (VQ) is applied in this step. In our experiment, Altera's DE2 board with Cyclone II FPGA is used to implement the recognition system which can recognize 64 words. The execution speed of the blocks in the speech recognition system is surveyed by calculating the number of clock cycles while executing each block. The recognition accuracies are also measured in different parameters of the system. These results in execution speed and recognition accuracy could help the designer to choose the best configurations in speech recognition on SoPC.

• Journal of Korea Multimedia Society
• /
• v.23 no.8
• /
• pp.927-939
• /
• 2020

Gait recognition can identify people's identity from a long distance, which is very important for improving the intelligence of the monitoring system. Among many human features, gait features have the advantages of being remotely available, robust, and secure. Traditional gait feature extraction, affected by the development of behavior recognition, can only rely on manual feature extraction, which cannot meet the needs of fine gait recognition. The emergence of deep convolutional neural networks has made researchers get rid of complex feature design engineering, and can automatically learn available features through data, which has been widely used. In this paper,conduct feature metric learning in the three-dimensional space by combining the three-dimensional convolution features of the gait sequence and the Siamese structure. This method can capture the information of spatial dimension and time dimension from the continuous periodic gait sequence, and further improve the accuracy and practicability of gait recognition.

• KSII Transactions on Internet and Information Systems (TIIS)
• /
• v.14 no.10
• /
• pp.4098-4116
• /
• 2020

Mobile devices such as smartphones are very attractive targets for augmented reality (AR) services, but their limited resources make it difficult to increase the number of objects to be recognized. When the recognition process is scaled to a large number of objects, it typically requires significant computation time and memory. Therefore, most large-scale mobile AR systems rely on a server to outsource recognition process to a high-performance PC, but this limits the scenarios available in the AR services. As a part of realizing large-scale standalone mobile AR, this paper presents a solution to the problem of accuracy, memory, and speed for large-scale object recognition. To this end, we design our own basic feature and realize spatial locality, selective feature extraction, rough pose estimation, and selective feature matching. Experiments are performed to verify the appropriateness of the proposed method for realizing large-scale standalone mobile AR in terms of efficiency and accuracy.

• 제어로봇시스템학회:학술대회논문집
• /
• 1991.10a
• /
• pp.704-706
• /
• 1991

In CAD/CAM system, many efforts are made to automate the converting process from drawling information to manufacturing Information. The most difficult step In this procedure is utilizing 2 dimensional drawing information In order to formulate 3 dimensional w&ling information. This paper emphasizes to mWe automatically series of convertirg steps which provide 3 dimensional wire frame, surface and solid modeling using feature recognition rules. With the standardization of design process and the recognition rule as preceding steps, it shows a good application tool to interface the design and manufacturing procedures in PC-Level CAD/CAM system.

• 제어로봇시스템학회:학술대회논문집
• /
• 2002.10a
• /
• pp.42.4-42
• /
• 2002

With the research of simplified neural networks, we propose an AND/OR neural network; a kind of brief, fast network Then, we present an OCR solution that equip the network in one-chip FPGA and design it by using HDL. We selected the representative hexadecimal character as the recognition feature class and used a Feature Vector Recognition Method in the statistic pattern recognition. The result feature vector was encoded into a 7 bit array and inputted into the AND/OR network to finish learning.

• Proceedings of the Korea Society of Design Studies Conference
• /
• 2001.05a
• /
• pp.62-63
• /
• 2001

• Journal of the Korean Institute of Telematics and Electronics
• /
• v.27 no.6
• /
• pp.929-936
• /
• 1990

This paper describes the method of the Korean character recognition by means of feature points extraction. Also, the preprocessing neural chip for noise elimination, smoothing, thinning and feature point extraction has been designs. The subpatterns were separated by means of advanced index algorithm using mask, and recognized by means of feature points classification. The separation of the Korean character subpatterns was abtained about 97%, and the recognition of the Korean characters was abtained about 95%. The preprocessing neural chip was simulated on SPICE and layouted by double CMOS 2\ulcorner design rule.