• Journal of Magnetics
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• 제20권2호
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• pp.148-154
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• 2015

48-V ISG (Integrated Starter Generator) system has attracted attention to improve the fuel efficiency of ICE (Internal Combustion Engine) vehicle. One of the key components that significantly affects the cost and performance of the 48-V ISG system is the motor. In an ISG motor, the core and copper loss make the motor efficiency change because the motor has a broad driving operated range and more diverse driving modes compared with other motors. When designing an ISG motor, the selection of an electrical steel sheet is important, because the electrical steel sheet directly influences the efficiency of the motor. In this paper, the efficiency of the ISG motor, considering core loss and copper loss, is analyzed by testing different types of electrical steel sheets with respect to the driving speed range and mode. Using the results of a finite element method (FEM) analysis, a method to select the electrical steel sheet is proposed. This method considers the cost of the steel sheet and the efficiency according to driving mode frequency during the design process of the motor. A wound rotor synchronous machine (WRSM) was applied to the ISG motor in this study.

• 한국통신학회논문지
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• 제16권12호
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• pp.1313-1323
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• 1991

본 논문에서는 객체 지향 프로그래밍을 이용한CAM(Content Addressable Memory)의 자동생성의 runplot 과정을 위한 생성기, 그래픽 디스플레이 툴(tool)을 제시하였다. 레이아웃 생성이나 그래픽 메뉴, 마우스 드라이버, 데이터 구조들을 기본 클래스들로 구성하여 기존의 절차적 언어보다 명료하고도 수정이 용이한 프로그램을 구성하였음을 보였다. CAM의 구조와 기본 회로 구성을 보였고 이들을 생성 하기위한 기본 클래스에 대해 설명하였다. 설계 규칙이나 공정에 독립적인 생성기 설계를 위해 기본 셀들을 사용자의 입력에 따라 변하도록 구성할 수 있는 매개변수화된 셀의 기법을 보였고 피치 매칭 기법을 이용한 배치·배선으로 레이아웃을 수행하였다. 끝으로 생성된 CIF의 디스플레이와 전체 run plot 과정을 위한 그래픽 메뉴의 구성을 설명하였다.

• 한국전자파학회논문지
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• 제18권1호
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• pp.90-95
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• 2007

LDR(Low Date Rate) UWB(Ultra Wide Band) 시스템에서 chaotic 신호를 이용한 OOK(On Off Keying) 통신 방법이 선택적 사항으로 채택되어 있다. 이 시스템에서 중요 회로 중에 하나인 chaotic 신호 발생 회로는 현재 대부분 아날로그 형태의 피드백 구조를 이용하고 있으나, 아날로그 형태의 피드백 구조는 공정 변화에 대한 취약점이 있어 양산성에 어려움이 있다. 이를 해결하기 위해 본 논문에서는 0.18 um CMOS 공정을 이용하여 디지털 구조의 PN-sequence를 응용하여 중심 주파수 4 GH에서 2 GHz의 대역폭을 갖는 Quasi-chaotic 신호 발생 회로를 설계 및 검증하였다.

• 한국정보통신설비학회:학술대회논문집
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• 한국정보통신설비학회 2005년도 하계학술대회
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• pp.159-165
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• 2005

The proposed optical transmitter is composed of FF(flip flop) , PLL (phase locked loop), reference clock generator, serializer and LD driver 10x250 Mb/s data arrays are translated to the 2.5 Gb/s data signal by serializer. In this case, 1 data bus is allocated usually as a reference clock for synchronization. In this proposed optical transmitter, 125 MHz reference clock is generated from 10x250 Mb/s data arrays by reference clock generator. From this method. absent of reference clock bus is available and more data transmission become possible. To achieve high speed operation, the serializer circuit is designed as two stacks. For 10:1 serialization, 10 clocks that have 1/10 lambda differences is essential, so the VCO (voltage controlled oscillator) composed of 10 delay buffers is designed. PLL is for runing at 250 MHz, and dual PFD(phase frequency detector) is adopted for fast locking time. The optical transmitter is designed by using 0.35 um CMOS technology.

• 대한전기학회논문지:전력기술부문A
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• 제48권1호
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• pp.52-60
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• 1999

This paper deals with a fault detection and isolation scheme for a DC motor driven centrifugal pump system. The emphasis is placed on the design and implementation of the residual generatorm, based on parity relation, that provides decision logic unit with residuals that will be further processed to detect and isolate three important faults in the system;brush fault, impeller fault, and the speed sensor fault. Two process faults are modelled as multiplicative type faults, while the sensor fault as an additive one. With multiplicative fault, the implementation of the residual generator needs the time varying transformation matrix that must be computed on-line. Typical implementation methods lack in generality because only a numerical approximation around the assumed fault levels is employed. In this paper, a new implementation method using well tranined neural network is proposed to improve the generality of the residual generator. Application results show that the fault detection and isolation scheme with the proposed residual generator effectively isolates three major faults in the centrifugal pump system even with a wide range of fault magnitude.

• Journal of Electrical Engineering and Technology
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• 제13권3호
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• pp.1346-1354
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• 2018

Quality of the power system depends upon the reliability of its components such as transformer, transmission lines, insulators, circuit breakers and isolators. The transient voltage due to internal or external reasons may affect the insulation level of the components. The insulation level of these components must be tested against these conditions. Different studies, testing of different electrical components against high voltage impulses and different industrial applications rely on the international manufactures for pulsed power generation and testing, that is quite expensive and large in size. In this paper a model of impulse voltage generator with capacitive load of pin type insulator is studied by simulation method and by an experimental setup. A ten stage high voltage impulse generator (HVIG) is designed and implemented for different applications. In this proposed model, the cost has been reduced by using small and cheap capacitors as an alternative for large and expensive ones while achieving the same effectiveness. Effect of the distributed capacitance in each stage is analyzed to prove the effectiveness of the model. Different values of front and tail resistances have been used to get IEC standard waveforms. Results reveal the effectiveness at reduced cost of the proposed model.

• 한국정보통신학회논문지
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• 제12권1호
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• pp.137-142
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• 2008

본 논문에서는 $Low-V_T$ 트랜지스터가 필요 없는 로직공정으로 Parasitic NPN BJT를 이용하여 저 전압에서 동작 가능한 밴드갭 기준전압 발생기 회로를 제안하였다. $0.18{\mu}m$ triple-well 공정을 사용한 BGR회로를 측정 한 결과 VREF의 평균전압은 0.72V $3{\sigma}$는 45.69mV로 양호하게 측정되었다.

• 한국정보통신학회:학술대회논문집
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• 한국해양정보통신학회 2009년도 춘계학술대회
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• pp.907-910
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• 2009

본 논문에서는 디지털 이미지의 무선 전송시 발생하는 에러를 제거 할 수 있는 오류 제어 부호화 기술 중 하나인 RS(Reed-Solomon) coding 중 Encoder의 FPGA 구현에 대한 논문이다. 여러 오류 제어 부호화 기술중 RS coding의 경우 비트가 아닌 심볼로 부호화를 하기 때문에 연집에러에 강한 것으로 알려져 있다. 본 논문에서는 RS coding중 최대 16바이트(Byte)의 에러를 정정할 수 있는 RS(255,223) 부호기를 FPGA 구현을 위해 Matlab을 이용하여 시뮬레이션을 하였다. 이때 사용한 영상은 JPG 파일을 이용하였다. 그리고 FPGA 구현을 위해 Xilinx사의 System Generator를 사용 하였다.

• 한국추진공학회지
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• 제21권1호
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• pp.104-111
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• 2017

탄두 신관에 사용되는 길이 25.4 mm, 직경 8.0 mm이고 행정길이 25.4 mm 이상에 대해 4.5 kgf의 추력을 제공하는 화약 벨로우즈를 새로이 개발하였다. BP/MTV 조성의 새로운 가스발생기를 개발하였으며, 화약 벨로우즈 작동시 압축되는 스프링의 길이를 측정하는 위력시험장치도 고안하였다. 새로 개발된 화약 벨로우즈가 요구조건을 만족하는지 검증하기 위해 감도시험과 위력시험을 수행하였다. 시험결과 새로 개발한 화약 벨로우즈는 요구조건을 충족하였으며, 탄두용 신관에 적용이 가능하다.

• Nuclear Engineering and Technology
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• 제51권5호
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• pp.1470-1476
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• 2019

The nuclear power plants in South Korea have been designed in accordance with the U.S. Regulatory Guide 1.60 (R.G 1.60) design spectrum of which the peak frequency range is 2-10 Hz. The characteristics of the earthquakes at the Korea nuclear power plant sites were observed to be closer to that of Central and Eastern United States (CEUS) than the R.G 1.60, which is a lower amplification in a low frequency range, and a higher amplification in a high frequency range. The possibility of failure for sensitive power plant components in the high frequency range has been considered and evaluated. In this study, in order to improve the reliability of nuclear plant and administrative control procedures, seismic tests of an emergency diesel generator (EDG) were conducted using a shaking table under both high and low frequency ranges. From the tests, oil/lubricant leaks from the bolt connections, the fuel filter and the fuel inlet were observed. Therefore, the check list of nuclear plant components after an earthquake should include bolt connections of EDG as well as anchor bolts.