• International Journal of Fuzzy Logic and Intelligent Systems
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• v.12 no.1
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• pp.20-28
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• 2012

We define a language $\mathcal{RS}$, a subclass of the scheduling language $\mathcal{RS}V$ (resource constrained project scheduling with variant processes). $\mathcal{RS}$ involves the determination of the starting times for ground activities of a project satisfying precedence and resource constraints, in order to minimize the total project duration. In $\mathcal{RS}$ ground activities and two structural symbols (operators) 'seq' and 'pll' are used to construct activity-terms representing scheduling problems. We consider three different variants for formalizing the $\mathcal{RS}$-scheduling problem, the optimizing variant, the number variant and the decision variant. Using the decision variant we show that the problem $\mathcal{RS}$ is $\mathcal{NP}$-complete. Further we show that the optimizing variant (or number variant) of the $\mathcal{RS}$-problem is computable in polynomial time iff the decision variant is computable in polynomial time.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2000.05a
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• pp.438-441
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• 2000

In this paper, Turbo rode is describing a performance near the Shannon's channel capacity limit. So, basic theory of turbo code and MAP,Log-MAP decoding algorithm was arranged. The foundation of this using VHDL, Log-MAP turbodecoder was implemented by Altera´s FLEX10K CPLD.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.31A no.5
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• pp.149-157
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• 1994

This paper Presents an algorithm for synthesis of sequential statements described at RT level VHDL. The proposed algorithm transforms sequential statements in VHDL into data-flow description consisting of concurrent statements by local and global dependency analysis and output dependency elimination. Transformation into concurrent statements makes it possible to reduce the cost of the synthesized hardwares, thus to get optimal synthesis results that will befit the designer 's intention. This algorithm has been implemented on VSYN and experimental results show that more compact gate-level hardwares are generated compared with Power View system from ViewLogic and Design Analyzer from Synopsys.

• Proceedings of the IEEK Conference
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• 2003.07e
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• pp.1787-1790
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• 2003

In this paper. we proposed a hardware(H/W) structure which can compress the video and embed the watermark in real time operation and implemented it into a FPGA platform using VHDL(VHSIC Hardware Description Language). All the image processing element to process both compression and reconstruction in a FPGA were considered each of them was mapped into H/W with the efficient structure for FPGA. The global operations of the designed H/W consists of the image compression with the watermarking and the reconstruction, and the watermarking operation is concurrently operated with the image compression. The implemented H/W used the 59％(12943) LAB(Logic Array Block) and 9％(28352) ESB(Embedded System Block) in the APEX20KC EP20K600CB652-7 FPGA chip of ALTERA, and stably operated in the 70㎒ clock frequency over. So we verified the real time operation, 60 fields/sec(30 frames/sec).

• Journal of the Korean Institute of Telematics and Electronics C
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• v.34C no.8
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• pp.22-38
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• 1997

This paper proposes a new VLSI architecture for morphological filters and presents its chip design and implementation. The proposed architecture can significantly reduce hardware costs compared with existing architecture by using a feedback loop path to reuse partial results and a decoder/encoder pair to detect maximum/minimum values. In addition, the proposed architecture requires one common architecture for both diltion and erosion and fewer number of operations. Moreover, it can be easily extended for larger size morphologica operations. We developed VHDL (VHSIC hardware description language) models, performed logic synthesis using the SYNOPSYS CAD tool. We used the SOG (sea-of-gate) cell library and implemented the actual chip. The total number of gates is only 2,667 and the clock frequency is 30 MHz that meets real-time image processing requirements.

• The Journal of Society for e-Business Studies
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• v.12 no.3
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• pp.133-150
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• 2007

In this paper we investigate a trend analysis service using Semantic Web technology in a news domain. The trend analysis service can provide more intelligent answers rather than the answer given In current news search engines since it can analyze the passage of time and the relation among news. In order to provide the trend analysis service, the capability of temporal reasoning is required, but the Semantic Web language such as OWL does not support the reasoning capability. Therefore, we propose a language TL-OWL(Temporal Web Ontology Language) extending OWL with the temporal reasoning.

• Proceedings of the Korean Information Science Society Conference
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• 2006.10b
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• pp.352-356
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• 2006

현존하는 추론 엔진들은 대부분 Tableaux 알고리즘 기반의 TBox의 최적화를 위한 연구를 진행하였다. 하지만 현실에서 대용량의 ABox를 추론하기 위한 유한한 시간 내에 결정 가능성을 보장하지 못한다. 따라서 실용성 있는 추론 엔진 효율을 위해서는 대용량 데이터를 가지는 ABox를 위한 최적화된 추론 기법이 필요하다. 본 논문에서는 OWL-DL 기반의 온톨로지(Ontology)를 데이터로그(Datalog)와 같은 규칙(Rule) 형태로 변형하여 관계형 데이터베이스와 같은 저장 시스템과 연동하기 위한 방법을 이용한다. 최종적으로 실세계의 환경에서의 데이터타입 속성(Datatype Property)이 포함된 SHIQ(D) 구성의 실용적인 추론 시스템을 수행하고자 한다. 따라서 OWL이 가지는 공리(Axiom)를 이용하여 데이터타입 속성이 포함된 규칙을 적용한 추론 방법에 대해서 제안하였다.

• Proceedings of the Korea Information Processing Society Conference
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• 2005.11a
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• pp.423-426
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• 2005

시맨틱 웹은 시스템이 더욱 효과적으로 정보를 액세스하고 이용이 가능하도록 하는 의미적 정보로서의 웹을 풍부하게 하는데 목적을 두며, 이는 온톨로지의 개념표현과 추론기능을 기반으로 한다. 온톨로지는 지식의 상호 커뮤니케이션을 위하여 개념적으로 명확하고 간결한 토대를 수립하기 위한 의미를 제공한다. 그런데 현재의 온톨로지 개발환경은 강력한 모델링 툴이나 경험이 풍부한 전문적인 온톨로지 구축 인력이 부족한 현실이다. 따라서 본 논문에서는 기존의 많은 개발자들에게 친숙해 있는 UML 또는 ER 도구를 이용하여 획득된 정보가 온톨로지 언어인 OWL의 정보와 커뮤니케이션이 가능하여 온톨로지 모델링 작업의 효율성을 높일 수 있도록 이들 사이의 메타모델 매핑변환을 시도하였다. 매핑의 기반에서는 DL을 이용하였다.

• International Journal of Fuzzy Logic and Intelligent Systems
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• v.13 no.3
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• pp.200-207
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• 2013

Petri Nets are a system description and analysis tool. Reachability is one of the most basic properties in Petri Net research. In a sense, reachability research is the foundation study for other dynamic properties of Petri Nets through which many problems involving Petri Nets can be described. Nowadays, there are two mature analysis methods-the matrix equation and the reachability tree. However, both methods are localized, i.e., it is difficult to find a general algorithm that can determine reachability for an arbitrary Petri Net, especially an unbounded Petri Net. This paper proposes and proves three propositions in order to present a subclass of a Petri Net, the live single-branch Petri Net, whose reachability is equivalent to the satisfiability of the state equation.

• 한국IT서비스학회:학술대회논문집
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• 2009.05a
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• pp.353-356
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• 2009

OWL 온톨로지의 확장 가능한(scalable) 추론(reasoning)에 대한 접근 방법으로 SQL로 구축된 논리 규칙을 관계형 데이터베이스에 저장되어있는 개체(individual)에 대한 사실(facts)과 공리(axioms)들에 적용하는 것이다. 예로서 미네르바(Minerva)는 서술 논리 프로그램(Description Logic Program, DLP)을 적용함으로써 ABox 추론을 수행한다. 본 연구에서는 관계형 데이터베이스를 기반으로 추론을 시도하며, 대규모 논리 규칙 집합을 사용한 추론을 시도한다. 뿐만 아니라, 특정 클래스에 속한 익명(anonymous)의 개체들과 개체들의 묵시적(implicit)인 관계성 추론을 시도하며, 필요한 경우 새로운 개체를 생성함으로써 명시화하여 추론을 시도한다. 더욱이, 추론의 논리 패러다임(paradigm)에서부터 데이터베이스 패러다임에 이르기까지 변화 시켜가면서 카디널리티(cardinality) 제약을 만족하는 개체들에 대한 제약적인 추정 추론을 시도하며, 벤치마크 테스트 결과 향상된 추론 능력을 얻을 수 있음을 보인다.