• 제목/요약/키워드: Deposition Height

검색결과 202건 처리시간 0.022초

Synthesis of Carbon Nanotubes by Using Inductively Coupled Plasma Chemical Vapor Deposition at Low Temperature

  • Kim, Young-Rae;Jang, In-Goo;Cho, Hyun-Jin;Jeon, Hong-Jun;Cho, Jung-Keun;Hwang, Ho-Soo;Kong, Byung-Yun;Lee, Nae-Sung
    • 한국정보디스플레이학회:학술대회논문집
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    • 한국정보디스플레이학회 2007년도 7th International Meeting on Information Display 제7권1호
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    • pp.768-771
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    • 2007
  • Carbon nanotubes (CNTs) were synthesized by inductively coupled plasma CVD at $450^{\circ}C$. CNTs were grown on the 1-nm-thick Fe-Ni-Co with $C_2H_2$ and $H_2$ at different pressures and plasma powers. CNTs were grown longer in height as the $H_{\alpha}/CH$ ratios became lower by decreasing plasma powers and increasing growth pressures.

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선택적 금속 전착에 대한 전해질 온도 및 전류밀도 영향분석 (The Characteristics of Electrolyte Temperature and Current Density on Selective Jet Electrodeposition)

  • 박찬규;김성빈;김영국;유봉영
    • 한국표면공학회지
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    • 제51권6호
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    • pp.400-404
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    • 2018
  • A metal 3D printer has been developed on its own to electrodeposit the localized area. Nozzles were used to selectively laminate the electrolytic plating method. To analyze the factors affecting the deposition, the stack height, thickness and surface roughness were experimentally analyzed according to the current density and the temperature of the electrolyte. Electrolytic temperature and current are electrodeposited when the deposition conditions are dominant over the etching conditions, but the thickness is kept constant. On the contrary, when the etching conditions are dominant, the electrodeposited shape is rather the etched. As a result, the uniformity of surface quality and electrodeposition rate could be improved by conducting experiments under constant conditions of electrolyte temperature and current density.

Research On Solutions To Slicing Errors In FDM 3D Printing Of Thin-walled Structures

  • QINGYUAN ZHANG;Byung-Chun Lee
    • International Journal of Internet, Broadcasting and Communication
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    • 제16권1호
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    • pp.176-181
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    • 2024
  • The desktop-level 3D printing machines makes it easier for independent designers to produce collectible models. Desktop 3D printers that use FDM (Fused Deposition Modeling) technology usually use a minimum nozzle diameter of 0.4mm. When using FDM printers to make Gunpla models, Thin slice structures are prone to slicing errors, which lead to deformation of printed objects and reduction in structural strength. This paper aims to analyze the printing model that produces errors, control a single variable among the three variables of slice layer height, slice wall thickness and filament type for comparative testing, and find a way to avoid gaps. To provide assistance for using FDM printers to build models containing thin-walled structures.

Temperature Analysis for the Point-Cell Source in the Vapor Deposition Process

  • Park, Jong-Wook;Kim, Sung-Cho;Hun Jung
    • Journal of Mechanical Science and Technology
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    • 제18권9호
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    • pp.1680-1688
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    • 2004
  • The information indicating device plays an important part in the information times. Recently, the classical CRT (Cathod Ray Tube) display is getting transferred to the LCD (Liquid Crystal Display) one which is a kind of the FPDs (Flat Panel Displays). The OLED (Organic Light Emitting Diodes) display of the FPDs has many advantages for the low power consumption, the luminescence in itself, the light weight, the thin thickness, the wide view angle, the fast response and so on as compared with the LCD one. The OLED has lately attracted considerable attention as the next generation device for the information indicators. And also it has already been applied for the outside panel of a mobile phone, and its demand will be gradually increased in the various fields. It is manufactured by the vapor deposition method in the vacuum state, and the uniformity of thin film on the substrate depends on the temperature distribution in the point-cell source. This paper describes the basic concepts that are obtained to design the point-cell source using the computational temperature analysis. The grids are generated using the module of AUTOHEXA in the ICEM CFD program and the temperature distributions are numerically obtained using the STAR-CD program. The temperature profiles are calculated for four cases, i.e., the charge rate for the source in the crucible, the ratio of diameter to height of the crucible, the ratio of interval to height of the heating bands, and the geometry modification for the basic crucible. As a result, the blowout phenomenon can be shown when the charge rate for the source increases. The temperature variation in the radial direction is decreased as the ratio of diameter to height is decreased and it is suggested that the thin film thickness can be uniformed. In case of using one heating band, the blowout can be shown as the higher temperature distribution in the center part of the source, and the clogging can appear in the top end of the crucible in the lower temperature. The phenomena of both the blowout and the clogging in the modified crucible with the nozzle-diffuser can be prevented because the temperature in the upper part of the crucible is higher than that of other parts and the temperature variation in the radial direction becomes small.

Effect of the catalyst deposition rates on the growth of carbon nanotubes

  • Ko, Jae-Sung;Choi, In-Sung;Lee, Nae-Sung
    • 한국전기전자재료학회:학술대회논문집
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    • 한국전기전자재료학회 2010년도 하계학술대회 논문집
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    • pp.264-264
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    • 2010
  • Single-walled carbon nanotubes (SWCNTs) were grown on a Si wafer by using thermal chemical vapor deposition (t-CVD). We investigated the effect of the catalyst deposition rate on the types of CNTs grown on the substrate. In general, smaller islands of catalyst occur by agglomeration of a catalyst layer upon annealing as the catalyst layer becomes thinner, which results in the growth of CNTs with smaller diameters. For the same thickness of catalyst, a slower deposition rate will cause a more uniformly thin catalyst layer, which will be agglomerated during annealing, producing smaller catalyst islands. Thus, we can expect that the smaller-diameter CNTs will grow on the catalyst deposited with a lower rate even for the same thickness of catalyst. The 0.5-nm-thick Fe served as a catalyst, underneath which Al was coated as a catalyst support as well as a diffusion barrier on the Si substrate. The catalyst layers were. coated by using thermal evaporation. The deposition rates of the Al and Fe layers varied to be 90, 180 sec/nm and 70, 140 sec/nm, respectively. We prepared the four different combinations of the deposition rates of the AI and Fe layers. CNTs were synthesized for 10 min by flowing 60 sccm of Ar and 60 sccm of $H_2$ as a carrier gas and 20 sccm of $C_2H_2$ as a feedstock at 95 torr and $810^{\circ}C$. The substrates were subject to annealing for 20 sec for every case to form small catalyst islands prior to CNT growth. As-grown CNTs were characterized by using field emission scanning electron microscopy, high resolution transmission electron microscopy, Raman spectroscopy, UV-Vis NIR spectroscopy, and atomic force microscopy. The fast deposition of both the Al and Fe layers gave rise to the growth of thin multiwalled CNTs with the height of ${\sim}680\;{\mu}m$ for 10 min while the slow deposition caused the growth of ${\sim}800\;{\mu}m$ high SWCNTs. Several radial breathing mode (RBM) peaks in the Raman spectra were observed at the Raman shifts of $113.3{\sim}281.3\;cm^{-1}$, implying the presence of SWCNTs (or double-walled CNTs) with the tube diameters 2.07~0.83 nm. The Raman spectra of the as-grown SWCNTs showed very low G/D peak intensity ratios, indicating their low defect concentrations.

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저온공정 n-InGaAs Schottky 접합의 구조적 특성 (Structural Analysis of Low Temperature Processed Schottky Contacts to n-InGaAs)

  • 이홍주
    • 한국전기전자재료학회논문지
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    • 제14권7호
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    • pp.533-538
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    • 2001
  • The barrier height is found to increase from 0.25 to 0.690 eV for Schottky contacts on n-InGaAs using deposition of Ag on a substrate cooled to 77K(LT). Surface analysis leads to an interface model for the LT diode in which there are oxide compounds of In:O and As:O between the metal and semiconductor, leading to behavior as a metal-insulator-semiconductor diode. The metal film deposited t LT has a finer and more uniform structure, as revealed by scanning electron microscopy and in situ metal layer resistance measurement. This increased uniformity is an additional reason for the barrier height improvement. In contrast, the diodes formed at room temperature exhibit poorer performance due to an unpassivated surface and non-uniform metal coverage on a microscopic level.

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절연막 형성 방법에 따른 다결정실리콘 캐패시터의 특성 (Characteristics of polysilicon capacitor as insulator formation method)

  • 노태문;이대우;김광수;강진영;이덕문
    • 전자공학회논문지A
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    • 제32A권7호
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    • pp.58-68
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    • 1995
  • Polysilicon capacitors with pyrogenic oxide and TEOX oxide as insulators were fabricated to develop capacitors which can be applied to analog CMOS IC, and the characteristics of the capacitors were compared with each other. The morphology of bottom polysilicon in pyrogenic oxide capacitor is degraded due to the generaged protuberances of the polysilicon grain during oxidataion. The polysilican capacitor with pyrogenic oxide of 57 nm thickness showed that the effective potential barrier height of 0.45 eV is much less than that of MOS capacitor (3.2 eV)when the top electrode is biased with a positive volgate. The morphology of the polysilicon capacitor with TEOS oxide, however, was not degraded during oxide deposition by LPCVD. The polysilicon capacitor with TEOS oxide of 54 nm thickness showed the effective potential barrier height of 1.28 eV when the top electrode is biased with a negative voltage. Therefore, it is concluded that the polysilicon capacitor with TEOS oxide is more applicable to analog CMOS IC than the pyrogenic oxide polysilicon capacitor.

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Electrical Characteristics of Metal/n-InGaAs Schottky Contacts Formed at Low Temperature

  • 이홍주
    • 한국전기전자재료학회논문지
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    • 제13권5호
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    • pp.365-370
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    • 2000
  • Schottky contacts on n-In$\_$0.53//Ga$\_$0.47//As have been made by metal deposition on substrates cooled to a temperature of 77K. The current-voltage and capacitance-voltage characteristics showed that the Schottky diodes formed at low temperature had a much improved barrier height compared to those formed at room temperature. The Schottky barrier height ø$\_$B/ was found to be increased from 0.2eV to 0.6eV with Ag metal. The saturation current density of the low temperature diode was about 4 orders smaller than for the room temperature diode. A current transport mechanism dominated by thermionic emission over the barrier for the low temperature diode was found from current-voltage-temperature measurement. Deep level transient spectroscopy studies exhibited a bulk electron trap at E$\_$c/-0.23eV. The low temperature process appears to reduce metal induced surface damage and may form an MIS (metal-insulator-semiconductor)-like structure at the interface.

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Fatigue Characteristics of PZT Thin Films Deposited by ECR-PECVD

  • Chung, Su-Ock;Lee, Won-Jong
    • Transactions on Electrical and Electronic Materials
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    • 제6권4호
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    • pp.177-185
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    • 2005
  • Fatigue characteristics of lead zirconate titanate (PZT) films deposited by electron cyclotron resonance plasma enhanced chemical vapor deposition (ECR-PECVD) were investigated. The fatigue characteristics were investigated with respect to PZT film thickness, domain structure, fatigue pulse height, temperature, electrode materials and electrode configurations. The used top and bottom electrode materials were Pt and $RuO_2$. In the fatigue characteristics with fatigue pulse height and PZT film thickness, the fatigue rates are independent of the applied fatigue pulse height at the electric field regions to saturate the P-E hysteresis and polarization $(P^*,\;P^A)$ characteristics. The unipolar and bipolar fatigue characteristics of PZT capacitors with four different electrode configurations $(Pt//Pt,\;Pt//RuO_2,\;RuO_2//Pt,\;and\;RuO_2//RuO_2)$ were also investigated. The polarization-shifts during the unipolar fatigue and the temperature dependence of fatigue rate suggest that the migration of charged defects should not be expected in our CVD-PZT films. It seems that the polarization degradations are attributed to the formation of charged defects only at the Pt/PZT interface during the domain switching. The charged defects pin the domain wall at the vicinity of Pt/PZT interface. When the top and bottom electrode configurations are of asymmetric $(Pt//RuO_2,\;RuO_2//Pt)$, the internal fields can be generated by the difference of charged defect densities between top and bottom interfaces.

전자 디바이스용 다이아몬드 박막의 제조 및 결정성장 특성 (Preparation of Diamond Thin film for Electric Device and Crystalline Growth)

  • 김규식;박수길;손원근
    • 대한전기학회:학술대회논문집
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    • 대한전기학회 2000년도 하계학술대회 논문집 C
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    • pp.1720-1723
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    • 2000
  • Boron doped conducting diamond thin film were grown on Si substrate by microwave plasma chemical vapor deposition from a gaseous feed of hydrogen, acetone/methanol and solid boron. The doping level of boron was controlled from 0ppm to $10^4$ppm (B/C). The Si substrate was tilted ca. 10$^{\circ}$ to make Si substrate have different height and temperature. Experimental results show that same condition but different temperature of Si substrate by height made different crystalline of diamond thin film. There were appeared 3$\sim$4 step of different crystalline morphology of diamond. To characterize the boron-doped diamond thin film, Raman spectroscopy was used for identification of crystallinity. To survey surface morphology, microscope was used. Grain size was changed gradually by different temperature due to different height. The Raman spectrum of film exhibited a sharp peak at 1334$cm^{-1}$, which is characteristic of crystalline diamond. The lower position of diamond film position, the more non-diamond component peak appeared near 1550$cm^{-1}$.

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