• Journal of the Korean Mathematical Society
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• v.32 no.2
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• pp.321-328
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• 1995

Ibragimov(1975) showed the central limit theorem and the invariance principle for $\rho$-mixing random variables satisfying $\sigma^2(n) = nh(n) \longrightarrow \infty$ and $E$\mid$\zeta_0$\mid$^{2+\delta} < \infty$ for some $\delta > 0$ where $\sigma^2(n)$ denotes the variance of the partial sum $S_n$ and h(n) is a slowly varying function.

• Journal of the Korean Society of Safety
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• v.16 no.1
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• pp.31-36
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• 2001

Surface crack growth characteristics and influence of the stress amplitude in rotary bending fatigue test were evaluated for annealed S35C steel, and than fractal dimensions of fatigue crack paths estimated using the box counting method. The following results that will be helpful to understand the fatigue crack growth mechanism were obtained. (1) Crack growth rate ds/dN and db/dN (s : half crack length at the surface crack, b : crack depth) depended on stress amplitude (${\Delta}{\sigma}/2$), stress intensity factor range (${\Delta}K_A, {\Delta}K_C$) and crack length. (2) At the effect area of 0.3 mm hole notch (s＜0.5 mm) crack growth rate did not depend on these factors. (3) The fractal dimensions (D) increased with stress amplitude (${\Delta}{\sigma}/2$) but decreased with cyclic number.

• Journal of Welding and Joining
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• v.28 no.2
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• pp.91-95
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• 2010

Stress distribution and deformation on the CT-type(Cross Tension type) spot welded lap joint subjected to out of plane tensile load were investigated by finite element method. Using the maximum principal stresses at the nugget edge obtained by FEM analysis, evaluated the fatigue strength of the CT-type spot welded lap joints having various dimensions and materials. and also, the influence of the geometrical parameters of CT-type spot welded lap joints on stress distribution and fatigue strength must be evaluated. thus, in this paper, ${\Delta}P-N_f$ curve were obtained by fatigue tests. Using these results, ${\Delta}P-N_f$ curve were systematically rearranged in the $\Delta\sigma-N_f$ relation with the hot spot stresses at the CT-type spot welded lab joints. It was found that the proposed $\Delta\sigma-N_f$ relation could provide a more reasonable fatigue design criterion for the CT-type spot welded lap joints.

• JSTS:Journal of Semiconductor Technology and Science
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• v.2 no.1
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• pp.41-48
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• 2002

This paper presents a 18-mW, 2.5-㎓ fractional-N frequency synthesizer with l-bit $4^{th}$-order interpolative delta-sigma ($\Delta{\;}$\sum$)modulator to suppress fractional spurious tones while reducing in-band phase noise. A fractional-N frequency synthesizer with a quadruple prescaler has been designed and implemented in a $0.5-\mu\textrm{m}$ 15-GHz $f_t$ BiCMOS. Synthesizing 2.1 GHzwith less than 200 Hz resolution, it exhibits an in-band phase noise of less than -85 dBc/Hz at 1 KHz offset frequency with a reference spur of -85 dBc and no fractional spurs. The synthesizer also shows phase noise of -139 dBc/Hz at an offset frequency of 1.2 MHz from a 2.1GHz center frequency.

• Journal of Welding and Joining
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• v.23 no.5
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• pp.49-54
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• 2005

The effective charge number and the critical current density of electromigration in eutetic SnPb and Pb Free $(SnAg_{3.8}Cu_{0.7)$ flip chip solder bumps are studied. The effective charge number of electromigration in eutectic SnPb solder is obtained as 34 and the critical current density is $j=0.169{\times}({\delta}_{\sigma}/{\delta}_x})\;A/cm^2,\;where\;({\delta}_{\sigma}/{\delta}_x})$ is the electromigration-induced compressive stress gradient along the length of the line. While the effect of electromigration in Pb free solder is much smaller than that in eutectic SnPb, the product of diffusivity and effective charge number $DZ^{\ast}$ has been assumed as $6.62{\times}10^{-11}$. The critical length for electromigration are also discussed.

• Journal of the Korean Mathematical Society
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• v.47 no.2
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• pp.263-275
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• 2010

Let {$X_n;n\;\geq\;1$} be a strictly stationary sequence of negatively associated random variables with mean zero and finite variance. Set $S_n\;=\;{\sum}^n_{k=1}X_k$, $M_n\;=\;max_{k{\leq}n}|S_k|$, $n\;{\geq}\;1$. Suppose $\sigma^2\;=\;EX^2_1+2{\sum}^\infty_{k=2}EX_1X_k$ (0 < $\sigma$ < $\infty$). We prove that for any b > -1/2, if $E|X|^{2+\delta}$(0<$\delta$$\leq$1), then $$lim\limits_{\varepsilon\searrow0}\varepsilon^{2b+1}\sum^{\infty}_{n=1}\frac{(loglogn)^{b-1/2}}{n^{3/2}logn}E\{M_n-\sigma\varepsilon\sqrt{2nloglogn}\}_+=\frac{2^{-1/2-b}{\sigma}E|N|^{2(b+1)}}{(b+1)(2b+1)}\sum^{\infty}_{k=0}\frac{(-1)^k}{(2k+1)^{2(b+1)}}$$ and for any b > -1/2, $$lim\limits_{\varepsilon\nearrow\infty}\varepsilon^{-2(b+1)}\sum^{\infty}_{n=1}\frac{(loglogn)^b}{n^{3/2}logn}E\{\sigma\varepsilon\sqrt{\frac{\pi^2n}{8loglogn}}-M_n\}_+=\frac{\Gamma(b+1/2)}{\sqrt{2}(b+1)}\sum^{\infty}_{k=0}\frac{(-1)^k}{(2k+1)^{2b+2'}}$$, where $\Gamma(\cdot)$ is the Gamma function and N stands for the standard normal random variable.

• Proceedings of the IEEK Conference
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• 2005.11a
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• pp.777-780
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• 2005

모바일 오디오 적용을 위한 저전력 ${\Sigma}{\Delta}$ Modulator 에 대한 설계와 layout 을 보였다. 전체 구조는 3 차 단일 피드백 루프이며, 해상도는 16bit 을 갖는다. 샘플링 주파수에 따른 Over-sampling Ratio 는 128(46kHz) 또는 64(96kHz) 가 되도록 하였다. 차동 구조를 사용한 3 차 ${\Sigma}{\Delta}$ modulator 내의 적분기에 사용된 Op-Amp 는 DC-Gain 을 높이기 위해서 Gain-boosting 기법이 적용되었다. ${\Sigma}{\Delta}$ modulator 의 기준 전압은 전류 모드 Band-Gap Reference 회로에서 공급이 되며, PVT(Process, Voltage, Temperature) 변화에 따른 기준 전압의 편차를 보정하기 위하여, binary 3bit 으로 선택하도록 하였다. DAC 에서 사용되는 단위 커패시터의 mismatch 에 의한 성능 감소를 막기 위해, DAC 신호의 경로를 임의적으로 바꿔주는 scrambler 회로를 이용하였다. 4bit Quantizer 내부의 비교기 회로는 고해상도를 갖도록 설계하였고, 16bit thermometer code 에서 4bit binary code 변환시 발생하는 에러를 줄이기 위해 thermometer-to-gray, gray-to-binary 인코딩 방법을 적용하였다. 0.18um CMOS standard logic 공정 내 thick oxide transistor(3.3V supply) 공정을 이용하였다. 입력 전압 범위는 2.2Vp-p,diff. 이며, Typical process, 3.3V supply, 50' C 시뮬레이션 조건에서 2Vpp,diff. 20kHz sine wave 를 입력으로 할 때 SNR 110dB, THD 는 -95dB 이상의 성능을 보였고, 전류 소모는 6.67mA 이다. 또한 전체 layout 크기는 가로 1100um, 세로 840um 이다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.1
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• pp.52-58
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• 2009

A low voltage, low power delta-sigma modulator is proposed for cardiac pacemaker applications. A cascade of delta-sigma modulator stages that employ a feedforward topology has been used to implement a high-resolution oversampling ADC under the low supply. An inverter-based switched-capacitor circuit technique is used for low-voltage operation and ultra-low power consumption. An experimental prototype of the proposed circuit has been implemented in a $0.35-{\mu}m$ CMOS process, and it achieves 61-dB SNDR, 63-dB SNR, and 65-dB DR for a 120-Hz signal bandwidth at 7.6-kHz sampling frequency. The power consumption is only 280 nW at 1-V power supply.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.11
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• pp.1-8
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• 2007

A wideband continuous-time sigma delta modulator for wireless application is implemented in 130nm CMOS. The SNR for small input signal is improved using a proposed adaptive quantizer which can effectively scale the quantization level. The modulator comprises a second-order loop filter for low power consumption, 4-bit quantizer and DAC for low jitter sensitivity and high linearity. Designed circuit achieves peak SNR of 51.36B with 10MHz signal Bandwidth and 320MHz sampling frequency dissipating 30mW.

• The Journal of the Korea institute of electronic communication sciences
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• v.7 no.4
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• pp.707-714
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• 2012

After a single-stage, second-order, multiple-feedback ${\Delta}-{\Sigma}$ modulator and a two-stage, second-order MASH ${\Delta}-{\Sigma}$ modulator were analyzed and simulated using Simulink and Matlab and their characteristics were compared, the following result was obtained: 1) The two ${\Delta}-{\Sigma}$ modulators do not have group delay distortion. 2) The characteristics of the noise shaping are nearly identical. As a result of the noise shaping, the power spectral densities have slope of 40 dB/dec. 3) There was no spurious tone. 4) The input range of the two modulators is from -1 to +1 in common. 5) Because the output of the two-stage MASH modulator is 2-bits (4-levels), design of frequency dividers and charge pumps of PLL are more demanding.