• JSTS:Journal of Semiconductor Technology and Science
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• v.6 no.2
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• pp.74-78
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• 2006

This paper presents a high-speed pulse-based flip-flop with pseudo MUX-type scan compatible with the conventional master-slave flip-flop with MUX-type scan. The proposed flip-flop was implemented as the standard cell library using Samsung 130nm HS technology. The data-to-output delay and power-delay-product of the proposed flip-flop are reduced by up to 59% and 49%, respectively. By using this flop-flop, ARM11 softcore has achieved the maximum 1GHz operating speed.

• The Korean Journal of Nuclear Medicine Technology
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• v.14 no.2
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• pp.55-59
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• 2010

Purpose: Renal excretion is the main route of FDG clearance in FDG PET/CT scan. Applying optimal method of renal excretion is very important for enhancing image quality and diagnostic accuracy. We evaluated several methods of renal excretion in FDG PET/CT scan. Materials and Methods: Thirty patients with normal renal function were prospectively included. Patients were divided into three group and undergone early and delayed FDG PET/CT scans. (1) Delay group; at 1 hour later of early scan, delayed scan was performed without additional hydration, (2) Hydration group; at 1 hour later of early scan, delayed scan was performed with additional oral hydration (700 mL of water), (3) Lasix group; lasix was administered at the end of early scan and dealyed scan was performed 30 min later. Early and delayed scans were compared to evaluate efficiency of renal excretion. Visual and quantitative analyses were performed by experienced physician and technologist of nuclear medicine. Results: On the visual analysis, renal excretion was the most evident in Lasix group followed by Hydration group. Delay group showed poor renal excretion. On the quantitative analysis, washout rates were $9.2{\pm}20.7%$, $28.1{\pm}22.8%$ and $29.5{\pm}23.1%$ for Delay, Hydration and Lasix groups, respectively. Conclusion: Administration of lasix was the best method for enhancing renal excretion. Delayed scan with hydration was also efficient method, but delayed scan without hydration was not adequate method.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.11
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• pp.105-114
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• 2000

Delay testing is essential for assurance of digital circuits as the speed and the density of the circuits improve greatly. However, delay faults in sequential circuits cannot be detected easily due to the existence of state registers. To overcome this difficulty a new test method and algorithm are devised which can be used for both stuck-at testing and delay testing. To apply the new test method, a new scan flip-flop is implemented. Experimental results on ISCAS 89 benchmark circuits show that the number of testable paths can be increased drastically over conventional scan techniques.

• 한국정보디스플레이학회:학술대회논문집
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• 2006.08a
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• pp.932-934
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• 2006

A relationship between discharge delay time and the aging method were investigated: A-Y (Address electrode - Scan electrode) aging and conventional X-Y(Common electrode - Scan electrode) aging with the variation of sustain voltage beyond self-erasing discharge. Although A-Y aging decreases discharge delay time, it has several drawbacks like non-uniformity of discharge, degradation of luminous efficiency and a color temperature. In a conventional aging condition which is carried out near the mid-margin voltage, discharge delay time is short in low voltage and high frequency condition. As an alternative to conventional voltage aging, high voltage aging is suggested which is carried out at self-erasing sustain voltage region. High voltage aging shows lower discharge delay time and fast aging speed than conventional voltage aging.

• Korean Journal of Radiology
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• v.1 no.3
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• pp.142-151
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• 2000

Objective: To determine the optimal scan timing for contrast-enhanced magnetic resonance angiography and to evaluate a new timing method based on the arteriovenous circulation time. Materials and Methods: Eighty-nine contrast-enhanced magnetic resonance angiographic examinations were performed mainly in the extremities. A 1.5T scanner with a 3-D turbo-FLASH sequence was used, and during each study, two consecutive arterial phases and one venous phase were acquired. Scan delay time was calculated from the time-intensity curve by the traditional (n = 48) and/or the new (n = 41) method. This latter was based on arteriovenous circulation time rather than peak arterial enhancement time, as used in the traditional method. The numbers of first-phase images showing a properly enhanced arterial phase were compared between the two methods. Results: Mean scan delay time was 5.4 sec longer with the new method than with the traditional. Properly enhanced first-phase images were found in 65% of cases (31/48) using the traditional timing method, and 95% (39/41) using the new method. When cases in which there was mismatch between the target vessel and the time-intensity curve acquisition site are excluded, erroneous acquisition occurred in seven cases with the traditional method, but in none with the new method. Conclusion: The calculation of scan delay time on the basis of arteriovenous circulation time provides better timing for arterial phase acquisition than the traditional method.

• Journal of KIISE:Computer Systems and Theory
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• v.34 no.2
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• pp.84-92
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• 2007

This paper proposes an interconnect delay fault test (IDFT) solution on boards and SoCs based on IEEE 1149.1 and IEEE P1500. A new IDFT system clock rising edge generator which forces output boundary scan cells to update test data at the rising edge of system clock and input boundary scan cells to capture the test data at the next rising edge of the system clock is introduced. Using this proposed circuit, IDFT for interconnects synchronized to different system clocks in frequency can be achieved efficiently. Moreover, the proposed IDFT technique does not require any modification of the boundary scan cells or the standard TAP controller and simplifies the test procedure and reduces the area overhead.

• Journal of KIISE:Computer Systems and Theory
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• v.26 no.8
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• pp.1024-1030
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• 1999

IEEE 1149.1 바운다리스캔은 보드 수준에서 고장점검 및 진단을 위한 테스트 설계기술이다. 그러나, 바운다리스캔 제어기의 특성상 테스트 패턴의 주입에서 관측까지 2.5 TCK가 소요되므로, 연결선상의 지연고장을 점검할 수 없다. 본 논문에서는 UpdateDR 신호를 변경하여, 테스트 패턴 주입에서 관측까지 1 TCK가 소요되게 함으로써, 지연고장 점검을 가능하게 하는 기술을 소개한다. 나아가서, 정적인 고장점검을 위한 테스트 패턴을 개선해 지연고장 점검까지 가능하게 하는, N개의 net에 대한 2 log(n+2) 의 새로운 테스트패턴도 제안한다. 설계와 시뮬레이션을 통해 지연고장 점검이 가능함을 확인하였다.Abstract IEEE 1149.1 Boundary-Scan is a testable design technique for the detection and diagnosis of faults on a board. However, since it takes 2.5TCKs to observe data launched from an output boundary scan cell due to inherent characteristics of the TAP controller, it is impossible to test delay defects on the interconnect nets. This paper introduces a new technique that postpones the activation of UpdateDR signal by 1.5 TCKs while complying with IEEE 1149.1 standard. Furthermore we have developed 2 log(n+2) , where N is the number of nets, interconnect test patterns to test delay faults in addition to the static interconnect faults. The validness of our approach is verified through the design and simulation.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.10
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• pp.728-734
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• 2001

Delay defects on I/O pads, interconnections of a board, or interconnections among embedded cores can not be tested with the current IEEE 1149.1 boundary scan design. This paper introduces a simple design technique which slightly modifies the TAP controller to test delay defects at system speed. Experimental design shows that the technique proposed requires much less area than a commercial approach.

• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.1
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• pp.71-78
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• 2013

In highly reliable and durable systems, failures due to aging might result in catastrophes. Aging monitoring techniques to prevent catastrophes by predicting such a failure are required. Aging can be monitored by performing a delay test at faster clocks than functional clock in field and checking the current delay state from the test clock frequencies at which the delay test is passed or failed. In this paper, we focus on test clock control scheme for a system-on-chip (SoC) with multiple clock domains. We describe limitations of existing at-speed test clock control methods and present an on-chip faster-than-at-speed test clock control scheme for intra/inter-clock domain test. Experimental results show our simulation results and area analysis. With a simple control scheme, with low area overhead, and without any modification of scan architecture, the proposed method enables faster-than-at-speed test of SoCs with multiple clock domains.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.19 no.8
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• pp.13-18
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• 2005

The variation of discharge characteristics of an ac PDP was observed with the charge of scan electrode driving circuit. Conventional scan electrode driving circuit provides two switches per one scan line, and the suggested one can be constituted by one switch per one scan line with the consideration of capacitive load characteristic of an ac PDP. To verify the workability of the suggested scheme, the performances of the ac PDP was investigated. The dynamic voltage margin was slightly decreased with the adoption of the suggested scheme, which is estimated to result from the misfiring of unselected discharge cells due to the deformation of voltage level of the neighboring scan electrode. In the observation of the delay characteristics of addressing discharge, the performances of the conventional circuit and the suggested one are assumed to be equivalent.