• Journal of Korean Society of Transportation
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• v.19 no.3
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• pp.75-88
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• 2001

Signal optimization model for alternative use of lanes at a signalized intersection with an stop-line added backward was presented in this paper. The simulation results shot-ed that the traffic fed from the stop-line passed the intersection in each specified phasing interval for left and through traffic. The experimental results indicated that the proposed model was much superior to traditional signal optimization methodology in reducing delay, fuel consumption, and disutility index for delay and stops. The effects for reducing delay were greater than those for doing fuel consumption and disutility index due to the added stop-line. The proposed model is expected to alleviate traffic congestion at intersections, both which have no left turn pocket, and which have large left turn volume. The model is recommended to adapted for intersections spaced long among them with no near driveway.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.43 no.4 s.310
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• pp.23-30
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• 2006

This paper presents design andd verification of a circuit that improves the control-operation problems of Stored Program Optical Computer (SPOC), which is an optical computer using $LiNbO_3$ optical switching element. Since the memory of SPOC takes the Delay Line Memory (DLM) architecture and instructions that are needless of operands should go though memory access stages, SPOC memory have problems; it takes immoderate access time and unnecessary operations are executed in Arithmetic Logical Unit (ALU) because desired operations can't be selectively executed. In this paper, improvement on circuit has been achieved by removing the memory access of instructions that are needless of operands by decoding instructions before locating operand. Unnecessary operations have been reduced by sending operands to some specific operational units, not to all the operational units in ALD. We show that total execution time of a program is minimized by using the Dual Instruction Register(DIR) architecture.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.23 no.7
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• pp.784-790
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• 2012

In this paper, an all-digital CMOS ultra-wideband(UWB) pulse generator for high band(6~10 GHz) frequency range is presented. The pulse generator is designed and implemented with extremely low power and low complexity. It is designed to meet the FCC spectral mask requirement by using Gaussian pulse shaping circuit and control the center frequency by using CMOS delay line with shunt capacitor. Measurement results show that the center frequency can be controlled from 4.5 GHz to 7.5 GHz and pulse width is 1.5 ns and pulse amplitude is 310 mV peak to peak at 10 MHz pulse repetition frequency(PRF). The circuit is implemented in 0.13 um CMOS process with a core area of only $182{\times}65um^2$ and dissipates the average power of 11.4 mW at an output buffer with 1.5-V supply voltage. However, the core consumes only 0.26 mW except for output buffer.

• Korean Journal of Remote Sensing
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• v.20 no.2
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• pp.117-124
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• 2004

A spherical earth surface is used for realistic analysis of the geometrical performance characteristics generated by 2-dimensional line-of-sight (LOS) tilt of the satellite imager using the Time Delay and Integration(TDI) technique. A 2-dimensional LOS tilt ever the spherical Earth surface is proposed to compensate geometric performance degradation caused by the satellite altitude decrease below the normal operation altitude. The compensation can be achieved by TDI re-match without degradation of modulation transfer function and with ground sample distance slightly increased. Effective methods of LOS tilt for the compensation are investigated. This study can be useful for mission assurance and flexibility in imager operation.

• Journal of the Korea Society of Computer and Information
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• v.18 no.8
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• pp.1-8
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• 2013

This paper proposes an effective parallel implementation of a physical modeling synthesis of guitar on the GPU environment. We used appropriate filter coefficients and adjusted the length of delay line for each open string to generate 44,100 six-polyphonic guitar sounds (E2, A2, D3, G4, B3, E4) by using physical modeling synthesis. In addition, we analyzed the physical modeling synthesis algorithm and observed that we can exploit parallelism inherent in the length of delay line. Thus, we assigned CUDA cores as many as the length of delay line and effectively implemented the physical modeling synthesis using GPU to achieve the highest performance. Experimental results indicated that synthetic guitar sounds using GPU were very similar to the original sounds when we compared their spectra. In addition, GPU achieved 68x and 3x better performance than high-performance TI DSP and CPU, respectively. Furthermore, this paper implemented and evaluated the performance of multi-GPU systems for the physical modeling algorithm.

• International Journal of Highway Engineering
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• v.9 no.4
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• pp.21-32
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• 2007

The linear traffic model(Vertical queueing model) that is adopted widely in traffic flow estimation assumes that all vehicles have the identical motion before joining a queue at the stop-line. Thus, a queue is supposed to form vertically not horizontally. Due to the simplicity of this model, the departure time of the leading vehicle is assumed to coincide with the start of effective green time. Thus, the delay estimates given by the Vertical queueing model is not always realistic. This paper explores a microscopic traffic model(a Kinematic Car-following model at Signalised intersections: a KCS traffic model) based on the one dimensional Kinematic equations in physics. A comparative evaluation in delay and sensitivity of delay difference between the KCS traffic model and the previously known Vertical queueing model is presented. The results show that the delay estimate in the Vertical queueing model is always greater than or equal to the KCS traffic model; however, the sensitivity of delay in the KCS traffic model is greater than the Vertical queueing model.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.28 no.3
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• pp.208-216
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• 2017

This paper presents the design method of an FMCW(frequency-modulated continuous-wave) altitude simulator which generates propagation delay signals according to target distances to test the radar altimeter. To improve the conventional RF method for creating delay signals, the simulator is designed by the RF-optics-RF method using optical delay lines. In addition, it is designed to simulate the Doppler shift and jamming that may occur in actual flight environment. In order to evaluate the performance of the developed simulator, the integration tests have been conducted with the radar altimeter. Through the test, we successfully verified the performance of the simulator.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.18 no.3
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• pp.206-211
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• 2005

The device makers want to make higher density chips on the wafer through scale-down. The change of WSix/poly-Si gate film thickness is one of the key issues under 100 nm device structure. As a new device etching process is applied, end point detection(EPD) time delay was occurred in DPS+ poly chamber of Applied Materials. This is a barrier of device shrink because EPD time delay made physical damage on the surface of gate oxide. To investigate the EPD time delay, the experimental test combined with OES(Optical Emission Spectroscopy) and SEM(Scanning Electron Microscopy) was performed using patterned wafers. As a result, a EPD delay time is reduced by a new chamber seasoning and a new wavelength line through plasma scan. Applying a new wavelength of 252 nm makes it successful to call corrected EPD in WSix/poly-Si stack-down gate etching in the DPS+ poly chamber for the current and next generation devices.

• Journal of electromagnetic engineering and science
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• v.16 no.1
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• pp.7-12
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• 2016

This paper presents the design of a negative group delay circuit (NGDC) using the filter synthesis approach. The proposed design method is based on a frequency transformation from a low-pass filter (LPF) to a bandstop filter (BSF). The predefined negative group delay (NGD) can be obtained by inserting resistors into resonators. To implement a circuit with a distributed transmission line, a circuit conversion technique is employed. Both theoretical and experimental results are provided for validating of the proposed approach. For NGD bandwidth and magnitude flatness enhancements, two second-order NGDCs with slightly different center frequencies are cascaded. In the experiment, group delay of $5.9{\pm}0.5ns$ and insertion loss of $39.95{\pm}0.5dB$ are obtained in the frequency range of 1.935-2.001 GHz.

• Journal of IKEEE
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• v.28 no.1
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• pp.1-5
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• 2024

To improve the performance of DRAM, it is essential to reduce sensing failures caused by mismatch in SA. Unlike flip failures, delay failures can be degraded, especially when high-speed operation is required, making it a critical consideration in the design of next-generation memory. While conventional SA operates with all transistors starting amplification simultaneously, SDSA selectively activates only two transistors that output BLB, thus alleviating offset. In this paper, we validate the superior performance of SDSA in mitigating delay failures through simulations. It was confirmed that SDSA exhibits approximately a 90 % reduction in delay failures compared to conventional SA.