• 전기전자학회논문지
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• 제11권4호
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• pp.235-238
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• 2007

2차원 소자 시뮬레이터인 TMA 메디치를 이용하여 필드링와 깊은 접합 필드링에 대해 연구하였다. 이온 주입될 위치를 미리 트랜치 식각을 시킴으로써 항복전압 특성을 향상시킬 수 있었다. 시뮬레이션 결과 기존 필드링의 항복전압대비 깊은 접합 필드링 항복전압은 약 30%의 증가를 보였다. 깊은 접합 필드링은 같은 면적을 차지하는 조건하에서 설계 및 제작이 비교적 용이하고, 표면 전하의 영향도 적은 것으로 나타났다. 본 논문에서는 여러 분석을 통해 깊은 접합 필드링의 향상된 특성을 논하였다.

• 전기전자학회논문지
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• 제24권2호
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• pp.619-625
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• 2020

본 논문에서는 Trench를 이용하여 기존 C-DMOSFET(Conventional DMOSFET)과 S-DMOSFET(Shielded DMOSFET) 구조보다 더 깊은 영역에 P+ shielding을 형성한 TS-DMOSFET(Trench Shielded DMOSFET) 구조를 제안하였으며 TCAD 시뮬레이션을 통해 C- 및 S-DMOSFET 구조와 전기적 특성을 비교하였다. 제안한 구조는 Source에 Trench를 형성한 후 도핑을 진행하므로 SiC 물질 특성과 관계없이 깊은 영역에 P+ shielding을 형성할 수 있다. 이로 인해 P-base에 인가되는 전압이 감소하여 리치스루 효과가 완화되었다. 그 결과 세 구조 모두 3.3kV의 항복 전압을 가질 때 제안한 구조의 온저항은 9.7mΩ㎠으로 C-DMOSFET과 S-DMOSFET의 온저항인 30.5mΩ㎠, 19.3mΩ㎠ 대비 각각 68%, 54% 개선된 온저항을 갖는다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제12권2호
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• pp.219-229
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• 2012

In the course of feasibility study the necessity of implementing electrochemical methods as an inline metrology technique to characterize semiconductor nano structures for a Deep Trench Dynamic Random Access Memory (DT-DRAM) (e.g. ultra shallow junctions USJ) was discussed. Hereby, the state of the art semiconductor technology on the advantages and disadvantages of the most recently used analytical techniques for characterization of nano electronic devices are mentioned. Various electrochemical methods, their measure relationship and correlations to physical quantities are explained. The most important issue of this paper is to prove the novel usefulness of the electrochemical micro cell in the semiconductor industry.

• 한국전기전자재료학회논문지
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• 제15권10호
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• pp.838-843
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• 2002

Chemical mechanical polishing(CMP) process has been widely used to planarize dielectric layers, which can be applied to the integrated circuits for deep sub-micron technology. The reverse moat etch process has been used for the shallow trench isolation(STI)-chemical mechanical polishing(CMP) process with conventional low selectivity slurries. Thus, the process became more complex, and the defects were seriously increased. In this paper, we studied the direct STI-CMP process without reverse moat etch step using high selectivity slurry(HSS). As our experimental results show, it was possible to achieve a global planarization without the complicated reverse moat process, the STI-CMP process could be dramatically simplified, and the defect level was reduced. Therefore the throughput, yield, and stability in the ULSI semiconductor device fabrication could be greatly improved.

• 한국전기전자재료학회논문지
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• 제13권9호
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• pp.729-734
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• 2000

Recently, Very Large Scale Integrated (VLSI) circuit & deep-submicron bulk Complementary Metal Oxide Semiconductor(CMOS) devices require gate electrode materials such as metal-silicide, Titanium-silicide for gate oxides. Many previous authors have researched the improvement sub-micron gate oxide quality. However, few have reported on the electrical quality and reliability on the ultra thin gate oxide. In this paper, at first, I recommand a novel shallow trench isolation structure to suppress the corner metal-oxide semiconductor field-effect transistor(MOSFET) inherent to shallow trench isolation for sub 0.1${\mu}{\textrm}{m}$ gate oxide. Different from using normal LOCOS technology deep-submicron CMOS devices using novel Shallow Trench Isolation(STI) technology have a unique"inverse narrow-channel effects"-when the channel width of the devices is scaled down, their threshold voltage is shrunk instead of increased as for the contribution of the channel edge current to the total channel current as the channel width is reduced. Secondly, Titanium silicide process clarified that fluorine contamination caused by the gate sidewall etching inhibits the silicidation reaction and accelerates agglomeration. To overcome these problems, a novel Two-step Deposited silicide(TDS) process has been developed. The key point of this process is the deposition and subsequent removal of titanium before silicidation. Based on the research, It is found that novel STI structure by the SEM, in addition to thermally stable silicide process was achieved. We also obtained the decrease threshold voltage value of the channel edge. resulting in the better improvement of the narrow channel effect. low sheet resistance and stress, and high threshold voltage. Besides, sheet resistance and stress value, rms(root mean square) by AFM were observed. On the electrical characteristics, low leakage current and trap density at the Si/SiO$_2$were confirmed by the high threshold voltage sub 0.1${\mu}{\textrm}{m}$ gate oxide.

• 대한전자공학회논문지SD
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• 제48권1호
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• pp.1-6
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• 2011

본 논문에서는 미세피치 프로브 카드 제작을 위한 S 모양의 일체형 외팔보 프로브 형성방법에 대하여 기술하였다. 마세 피치 프로브를 위하여 Deep RIE etching을 이용하여 실리콘 트렌치 안에 일체형 프로브 빔과 탑을 형성하는 방법을 사용하였고, 피라미드 팁의 형성을 위하여 KOH 및 TMAH 습식식각을 이용하였으며, 습식식각시 방향성을 가지는 실리콘 웨이퍼에서도 휘어진 형태의 프로브 빔을 형성할 수 있는 건식 식각 및 습식식각 방법을 제시하였다. 따라서 제작된 외팔보 형태의 프로브는 디렘(DRAM), 플레시 메모리 (Flash memory) 용 프로브 카드 제작에 사용될 뿐만 아니라 RF 소자용 프로브 카드, 아이씨 테스트 소켓 (IC test socket)용 프로브 탐침에도 사용 될 것이다.

• 암석학회지
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• 제1권1호
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• pp.71-84
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• 1992

이 연구는 서 태평양의 서부 캐롤라인 해령과 얍 해구-호상열도계에서 준설된 대표적인 13개 해저 현무암류의 암석기재 및 광물화학적 특징을 보고하고, 단사휘석 반정의 화학성분을 이용하여 암석의 화학적 특징 및 지구조 환경을 추론하는 기초 자료를 제공한다. 감람석 반정은 분석된 시료에 따라 약간의 차이는 있지만 F $o_{86-80}$거 성분을 가지며, 사장석 반정은 전체적으로 A $n_{90-55}$의 바이토나이트-라브라도라이트에 해당한다. 단사휘석 반정은 아톨-기요 시료에서 티탄살라이트, 트라프-뱅크 시료에서 투휘석-보통휘석, 해구-호상열도 시료에서 엔다이옵사이드에 해당되어 산출 지역에 따라 각기 성분이 다름을 보인다. 이들 단사휘석의 성분으로 부터 암석의 화학적 특징 및 지구조 환경을 유추하면 (Leterrier et al., 1982): (1) 서부 캐롤라인 해령의 아톨-기요 시료는 판내부 환경의 알칼리암의 특징을 가져, 이는 열점과 관련되어 형성된 동부 캐롤라인 해령의 연장에 해당함을 의미하고, (2) 현재 화성활동이 없는 얍 해구-호상열도 시료는 전형적인 조산대 솔리아이트에 속하여 고기의 호상열도의 형성과 관련된 마그마 활동이 있었음을 나타낸다. 그러나, (3) 트라프-뱅크 시료는 단사휘석의 성분을 이용한 지구조 분류도에서 서로 중첩되어 정확히 구분하기 어려운데, 이는 이들의 성인이 복잡함을 시사하는 것으로 여겨진다.

• 대한기계학회논문집B
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• 제31권3호
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• pp.225-233
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• 2007

The growth of GaN on the patterned substances has proven favorable to achieve thick, crack-free GaN layers. In this paper, numerical modeling of transport and reaction of species is performed to estimate the growth rate of GaN from tile reaction of TMG(trimethly-gallium) and ammonia. GaN growth rate was estimated through the model analysis including the effect of species velocity, thermal convection and chemical reaction, and thermal condition for the uniform deposition was to be presented. The effect of shape and construction of microscopic pattern was also investigated using a simulator to perform surface analysis, and a review was done on the quantitative thickness and shape in making GaN layer on the pattern. Quantitative analysis was especially performed about the shape of reactor geometry, periodicity of pattern and flow conditions which decisively affect the quality of crystal growth. It was found that the conformal deposition could be obtained with the inclination of trench ${\Theta}>125^{\circ}$. The aspect ratio was sensitive to the void formation inside trench and the void located deep in trench with increased aspect ratio.

• 한국측량학회지
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• 제33권3호
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• pp.181-192
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• 2015

Bathymetry change due to the 2011 Tohoku (M9.0) earthquake was investigated through satellite altimetry-derived free-air gravity anomalies (SAFAGA) and shipborne measurements. The earthquake occurred at the plate boundaries near the northeastern coast of Japan, where the oceanic plate subducts beneath the continental plate along deep-sea trench. Data analyzed in this study include SAFAGA from Scripps Institution of Oceanography (SIO), shipborne bathymetry (SB) from the U.S. National Geophysical Data Center (NGDC) and the Japan Agency for Marine-Earth-Science And Technology (JAMSTEC). To estimate the bathymetry change, a reference bathymetry before the earthquake was predicted by gravity-geologic method (GGM) and Smith & Sandwell’s (SAS) method. In comparison with the bathymetry models before the earthquake, GGM bathymetry model generated by a tuning density contrast of 17.04 g/cm³ by downward continuation method was selected because it shows better bathymetry in the short wavelength below about 6 km. From the results, remarkable bathymetry change of about ±50 m was found on the west side of the Japan Trench caused by the earthquake.

• ETRI Journal
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• 제25권3호
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• pp.195-202
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• 2003

This paper proposes a new LDMOSFET structure with a trenched sinker for high-power RF amplifiers. Using a low-temperature, deep-trench technology, we succeeded in drastically shrinking the sinker area to one-third the size of the conventional diffusion-type structure. The RF performance of the proposed device with a channel width of 5 mm showed a small signal gain of 16.5 dB and a maximum peak power of 32 dBm with a power-added efficiency of 25% at 2 GHz. Furthermore, the trench sinker, which was applied to the guard ring to suppress coupling between inductors, showed an excellent blocking performance below -40 dB at a frequency of up to 20 GHz. These results confirm that the proposed trenched sinker should be an effective technology both as a compact sinker for RF power devices and as a guard ring against coupling.