• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.26 no.10
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• pp.713-719
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• 2013

Power MOSFET operate voltage-driven devices, design to control the large power switching device for power supply, converter, motor control, etc. We have optimal designed planar and trench gate power MOSFET for high breakdown voltage and low on resistance. When we have designed $6,580{\mu}m{\times}5,680{\mu}m$ of chip size and 20 A current, on resistance of trench gate power MOSFET was low than planar gate power MOSFET. The on state voltage of trench gate power MOSFET was improved from 4.35 V to 3.7 V. At the same time, we have designed unified field limit ring for trench gate power MOFET. It is Junction Termination Edge type. As a result, we have obtained chip shrink effect and low on resistance because conventional field limit ring was convert to unify.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2004.07a
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• pp.421-424
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• 2004

As the deep sub-micron devices are recently integrated high package density, novel process method for sub $0.1{\mu}m$ devices is required to get the superior thin gate oxide characteristics and reliability. However, few have reported on the electrical quality and reliability on the thin gate oxide. In this paper I will recommand a novel shallow trench isolation structure for thin gate oxide $30{\AA}$ of deep sub-micron devices. Different from using normal LOCOS technology, novel shallow trench isolation have a unique 'inverse narrow channel effects' when the channel width of the devices is scaled down shallow trench isolation has less encroachment into the active device area. Based on the research, I could confirm the successful fabrication of shallow trench isolation(STI) structure by the SEM, in addition to thermally stable silicide process was achiever. I also obtained the decrease threshold voltage value of the channel edge and the contact resistance of $13.2[\Omega/cont.]$ at $0.3{\times}0.3{\mu}m^2$. The reliability was measured from dielectric breakdown time, shallow trench isolation structure had tile stable value of $25[%]{\sim}90[%]$ more than 55[sec].

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.27 no.8
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• pp.501-504
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• 2014

This paper was developed and described core-process to implement low on resistance which was the most important characteristics of SJ (super junction) MOSFET. Firstly, using process-simulation, SJ MOSFET optimal structure was set and developed its process flow chart by repeated simulation. Following process flow, gate level process was performed. And source and drain level process was similar to genral planar MOSFET, so the process was the same as the general planar MOSFET. And then to develop deep trench process which was main process of the whole process, after finishing photo mask process, we developed deep trench process. We expected that developed process was necessary to develop SJ MOSFET for automobile semiconductor.

• Proceedings of the KIEE Conference
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• 1998.11c
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• pp.723-725
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• 1998

STI CMP process are substituting gradually for LOCOS(Local Oxidation of Silicon) process to be available below sub-0.5um technology and to get planarized. The other hand, STI CMP process(especially STI CMP with RIE etch back process) has some kinds of defect like Nitride residue, Torn Oxide defect, etc. In this paper, we studied how to reduce Torn Oxide defects after STI CMP with RIE etch back process. Although Torn Oxide defects which occur on Oxide on Trench area is not deep and not sever, Torn oxide defects on Moat area is sometimes very deep and makes the yield loss. We did test on pattern wafers witch go through Trench process, APCVD process, and RIE etch back process by using an REC 472 polisher, IC1000/SUV A4 PAD and KOH base slurry to reduce the number of torn defects and to study what is the root causes of torn oxide defects.

• Journal of the Korean Vacuum Society
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• v.11 no.4
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• pp.235-239
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• 2002

A new method for deep trench isolation using selective growth of polycrystalline silicon is proposed. In this method, trench filling is performed by forming polysilicon-inner sidewalls within the trench, and then selectively growing them by reduced chemical vapor deposition using $SiH_2C1_2$gas at $1100^{\circ}C$. The surface profiles of filled trenches are determined mainly by the initial depth of inner sidewalls and the total thickness of selective growth. No chemical mechanical polishing(CMP) process is needed in this new method, which makes the process flow simpler and more reliable in comparison with the conventional method using CMP process.

• Transactions on Electrical and Electronic Materials
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• v.17 no.4
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• pp.222-226
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• 2016

This paper investigated the trench process, unified field limit ring, and other products for the development of a 500 V-level unified trench gate power MOSFET. The optimal base chemistry for the device was found to be SF₆. In SEM analysis, the step process of the trench gate and field limit ring showed outstanding process results. After finalizing device design, its electrical characteristics were compared and contrasted with those of a planar device. It was shown that, although both devices maintained a breakdown voltage of 500 V, the Vth and on-state voltage drop characteristics were better than those of the planar type.

• Journal of the Korean Geotechnical Society
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• v.18 no.4
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• pp.239-248
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• 2002

Bentonite slurries in a slurry wall construction must fulfill a stabilizing function by forming impermeable membrane (surface cake and penetrated cake) on the excavated soil faces. Thus problems are occurring in practice for the construction of diaphram walls and cut-off walls with a low permeability for wastes disposal areas in some deep excavations or different grounds. In this paper, the fundamental mechanics of fluid loss and filter cake formation in various soil beds are investigated using large scale laboratory apparatus. The sealing efficiency of filter cake from the large scale tests and the significance of fluid loss in a slurry trench are utilized for practical situation as a recommended design procedure.

• Korean Journal of Fisheries and Aquatic Sciences
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• v.39 no.spc1
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• pp.203-213
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• 2006

The spatial patterns of meiobenthic communities in deep-sea sediment were examined. Sediment samples for analyzing of meiobenthic community structure were collected using a remote operated vehicle (ROV), multiple corer TV grab at 20 stations at five sites. In all, 15 meiofauna groups were recorded. Nematodes were the most abundant taxon. Benthic foraminiferans, harpacticoid copepods, polychaetes, and crustacean naupii were also dominant groups at all sites. The total meiofauna density at the study sites varied from 49 to 419 ind./$10cm^2$. The maximum density was recorded at a site located in Challenger Deep in the Mariana trench where simple benthic foraminifera with organic walls flourish. These distinctive taxa seem to be characteristic of the deepest ocean depths. Active hydrothermal sediments contain up to 150 harpacticoid copepods per $10cm^2$ of sediment. In a inactive ridge sediments, devoid of macrofaunal organisms:, the abundance of harpacticoid copepods never exceeded 15 ind./$10cm^2$. Multivariate analysis (multidimensional scaling) revealed significant differences in community structure among the three regions; near an active hydrothermal vent, in the deepest ocean depths and at typical deep-sea bed sites.

• 한국석유지질학회:학술대회논문집
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• autumn
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• pp.35-35
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• 2000

• 한국석유지질학회:학술대회논문집
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• autumn
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• pp.34-34
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• 2000