• 한국전기전자재료학회논문지
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• 제14권2호
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• pp.117-122
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• 2001

In this paper, we report on photoelectrochemical etching process of 6H-SiC semiconductor wafer. The etching was performed in two-step process; anodization of SiC surface to form a deep porous layer and thermal oxidation followed by an HF dip. Etch rate of about 615${\AA}$/min was obtained during the anodization using a dilute HF(1.4wt% in H$_2$O) electrolyte with the etching potential of 3.0V. The etching rate was increased with the bias voltage. It was also found out that the adition of appropriate portion of H$_2$O$_2$ into the HF solution improves the etching rate. The etching process resulted in a higherly anisotropic etching characteristics and showed to have a potential for the fabrication of SiC devices with a novel design.

• 한국재료학회지
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• 제2권5호
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• pp.383-386
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• 1992

(100) 실리콘 기판에 대해 깊온 비등방성 식각을 행한 경우 식각면의 가장자리에 존재하는 욜균일성은 식각 계면의 격자결함과 기계적 응력에 의한 것임을 판찰할 수 있었다.

• Journal of the Optical Society of Korea
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• 제18권3호
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• pp.283-287
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• 2014

Square lattice nano-hole arrays with diameters and periodicities of 200 and 500 nm, respectively, are fabricated on InGaN/GaN blue light emitting diodes (LEDs) using electron-beam lithography and inductively coupled plasma reactive ion etching processes. Cathodoluminescence (CL) investigations show that light emission intensity from the LEDs with the nano-hole arrays is enhanced compared to that from the planar sample. The CL intensity enhancement factor decreases when the nano-holes penetrate into the multiple quantum wells (MQWs) due to the plasma-induced damage and the residues. Wet chemical treatment using KOH solution is found to be an effective method for light extraction from the nano-patterned LEDs, especially, when the nano-holes penetrate into the MQWs. About 4-fold CL intensity enhancement factor is achieved by the KOH treatments after the dry etching for the sample with a 250-nm deep nano-hole array.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2014년도 제46회 동계 정기학술대회 초록집
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• pp.454-454
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• 2014

Silicon microwire array is one of the promising platforms as a means for developing highly efficient solar cells thanks to the enhanced light trapping efficiency. Among the various fabrication methods of microstructures, deep reactive ion etching (DRIE) process has been extensively used in fabrication of high aspect ratio microwire arrays. In this presentation, we show precisely controlled Si microwire arrays by tuning the DRIE process conditions. A periodic microdisk arrays were patterned on 4-inch Si wafer (p-type, $1{\sim}10{\Omega}cm$) using photolithography. After developing the pattern, 150-nm-thick Al was deposited and lifted-off to leave Al microdisk arrays on the starting Si wafer. Periodic Al microdisk arrays (diameter of $2{\mu}m$ and periodic distance of $2{\mu}m$) were used as an etch mask. A DRIE process (Tegal 200) is used for anisotropic deep silicon etching at room temperature. During the process, $SF_6$ and $C_4F_8$ gases were used for the etching and surface passivation, respectively. The length and shape of microwire arrays were controlled by etching time and $SF_6/C_4F_8$ ratio. By adjusting $SF_6/C_4F_8$ gas ratio, the shape of Si microwire can be controlled, resulting in the formation of tapered or vertical microwires. After DRIE process, the residual polymer and etching damage on the surface of the microwires were removed using piranha solution ($H_2SO_4:H_2O_2=4:1$) followed by thermal oxidation ($900^{\circ}C$, 40 min). The oxide layer formed through the thermal oxidation was etched by diluted hydrofluoric acid (1 wt% HF). The surface morphology of a Si microwire arrays was characterized by field-emission scanning electron microscopy (FE-SEM, Hitachi S-4800). Optical reflection measurements were performed over 300~1100 nm wavelengths using a UV-Vis/NIR spectrophotometer (Cary 5000, Agilent) in which a 60 mm integrating sphere (Labsphere) is equipped to account for total light (diffuse and specular) reflected from the samples. The total reflection by the microwire arrays sample was reduced from 20 % to 10 % of the incident light over the visible region when the length of the microwire was increased from $10{\mu}m$ to $30{\mu}m$.

• 센서학회지
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• 제19권2호
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• pp.137-141
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• 2010

In this paper, we fabricated silicon piezoresistive pressure sensor with dry etching technology which used Deep-RIE and etching delay technology which used SOI(silicon-on-insulator) wafer. We improved pressure sensor offset and its temperature dependence by removing oxidation layer of SOI wafer which was used for dry etching delay layer. Sensitivity of the fabricated pressure sensor was about 0.56 mV/V${\cdot}$kPa at 10 kPa full-scale, and nonlinearity of the fabricated pressure sensor was less than 2 %F.S. The zero off-set change rate was less than 0.6 %F.S.

• JSTS:Journal of Semiconductor Technology and Science
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• 제8권2호
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• pp.121-127
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• 2008

This paper presents design and fabrication of optimized geometry structure of electrostatic inkjet head. In order to verify effect of geometry shape, we simulate electric field intensity according to the head structure. The electric field strength increases linearly with increasing height of the micro nozzle. As the nozzle diameter decreases, the electric field along the periphery of the meniscus can be more concentrated. We design and fabricate the electrostatic inkjet heads, hole type and pole type, with optimized structure. It was fabricated using thick-thermal oxidation and silicon micromachining technique such as the deep reactive ion etching (DRIE) and chemical wet etching process. It is verified experimentally that the use of the MEMS inkjet head allows a stable and sustainable micro-dripping mode of droplet ejection. A stable micro dripping mode of ejection is observed under the voltages 2.5 kV and droplet diameter is $10\;{\mu}m$.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2012년도 제42회 동계 정기 학술대회 초록집
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• pp.296-296
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• 2012

LCD panel 검사를 위한 Probe unit은 대형 TV 및 모바일용 스마트폰을 중심으로 각광을 받고 있는 소모성 부품으로 최근 pitch의 미세패턴화가 급속히 진행되고 있다. 본 연구에서는 Slit Wafer 제작 공정을 최적화하기 위해 25 um pitch의 마스크를 설계, 제작하였다. 단공과 장공을 staggered 형태로 배열하여 25 um/25 um line/space pitch로 설계하였다. 또한 단위실험을 위해 직접 25 um pitch로 설계하여, 동일한 실험조건을 적용하여 최적 조건을 찾고자 하였다. 반응변수는 Etch rate 및 profile angle로 결정하였으며, 약 200~400 um 에칭된 slit의 상단과 하단의 폭, 그리고 식각깊이를 SEM 측정사진을 통해 정한 후 etch rate 및 profile angle을 결정하였다. 인자는 식각속도 및 wall의 각도를 결정하는 식각 및 passivation 가스의 유량, chamber 압력(etching/passivation), 식각시간 등으로 정하였으며, 이들의 최대값과 최소값 2 수준으로 실험계획을 설계하였다. 식각 조건에 따라 8회의 실험을 수행하였다. 가스의 유량은 SF6 400 sccm, C4F8 400 sccm, 식각 싸이클 시간은 5.2~10.4 sec, passivation 싸이클시간 4 sec로 하였으며, 압력은 식각시 7.5 Pa, passivation 시 10 Pa로 할 경우가 가장 sharp하게 나타났다. Coil power 와 platen power는 각각 2.6 KW, 0.14 KW로 하였으며, 최적화를 위한 인자의 값들은 이 범위에서 조절하였다. 이러한 인자의 조건 조절을 통해 etch rate는 5.6 um/min~6.4 um/min, $88.9{\sim}89.1^{\circ}$의 profile angle을 얻을 수 있었다.

• 대한금속재료학회지
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• 제48권11호
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• pp.1028-1034
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• 2010

In the development of 3D package, through silicon via (TSV) formation technology by using deep reactive ion etching (DRIE) is one of the key processes. We performed the Bosch process, which consists of sequentially alternating the etch and passivation steps using $SF_6$ with $O_2$ and $C_4F_8$ plasma, respectively. We investigated the effect of changing variables on vias: the gas flow time, the ratio of $O_2$ gas, source and bias power, and process time. Each parameter plays a critical role in obtaining a specified via profile. Analysis of via profiles shows that the gas flow time is the most critical process parameter. A high source power accelerated more etchant species fluorine ions toward the silicon wafer and improved their directionality. With $O_2$ gas addition, there is an optimized condition to form the desired vertical interconnection. Overall, the etching rate decreased when the process time was longer.

• 대한기계학회:학술대회논문집
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• 대한기계학회 2001년도 춘계학술대회논문집E
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• pp.169-174
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• 2001

This paper reports on the development of high aspect ratio structure and 3-D integrated process for MEMS-based micro gas turbines. To manufacture high aspect ratio structures, Deep Reactive Ion Etching (DRIE) process have been developed and optimized. Specially, in this study, structures with aspect ratios greater than 10 were fabricated. Also, wafer direct bonding and Infra-Red (IR) camera bonding inspection systems have been developed. Moreover, using glass/silicon wafer direct bonding, we optimized the 3-D integrated process.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2001년도 하계학술대회 논문집
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• pp.741-744
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• 2001

This paper described on the fabrication of microstructures by DRIE(Deep Reactive Ion Etching). SOI(Si-on-insulator) electric devices with buried cavities are fabricated by SDB technology and electrochemical etch-stop. The cavity was fabricated the upper handling wafer by Si anisotropic etch technique. SDB process was performed to seal the fabricated cavity under vacuum condition at -760 mm Hg. In the SDB process, captured air and moisture inside of the cavities were removed by making channels towards outside. After annealing(1000$^{\circ}C$, 60 min.), the SDB SOI structure was thinned by electrochemical etch-stop. Finally, it was fabricated microstructures by DRIE as well as a accurate thickness control and a good flatness.