• Proceedings of the IEEK Conference
• /
• 2005.11a
• /
• pp.797-800
• /
• 2005

In this paper, the designed 10-bit current steering data driving circuit consists of bias circuits, shift registers, data and line latches, level shifters, and 10-bit D/A converters. This data driving circuit can improve image quality, driving speed, and can reduce process error, DNL error, and glitch noise. To reduce current cells, the 10-bit D/A converter was designed 3+3+4 hybrid type. As a result 49 current cells are decreased. The transient analysis shows that currents flows a few of mA in data line and the currents have 1024 gray levels of current values. Total circuits are designed for 10 ${\mu}s$ speed. Thus the designed 10-bit current steering data driving circuit can be usable in HDTV/XGA AMOLED displays. These data driving circuits are designed for 0.35 ${\mu}m$ CMOS process at 3.3 V and 18 V supply voltage and simulated with HSPICE..

• Journal of the Korean Society for Precision Engineering
• /
• v.19 no.10
• /
• pp.139-146
• /
• 2002

We developed a motion capture system to utilize informations on the human walking motion. The system is composed of the mechanical and electronic devices to obtain the joint angle data and the software to analyze the obtained data and to transform the data into the input for a biped walking robot. The mechanical system is composed of a pair of links with 3 revolute joints, on which potentiometers are attached on joint axes to sense rotation angles. Analog signals from potentiometers are transformed into the digital data through the low pass filter and the A/D converter, and then which are stored at the computer. We analyzed the walking characteristics by applying FFT to the digital data, and then performed a 3-D computer simulation using the data. Finally, We apply the processed data to a biped walking robot.

• Journal of the Institute of Convergence Signal Processing
• /
• v.4 no.2
• /
• pp.61-69
• /
• 2003

In this paper, we developed the U parameter test system which inspects the property of DC parameter for semiconductor products. The developed system is interfaced by IBM-PC. It is consisted of CPLD part, ADC (Analogue to Digital Converter), DAC (Digital to Analogue Converter), voltage/current source, variable resistor and measurement part. In the proposed system, we have designed the constant voltage source and the constant current source in a part. The CPLD part is designed by VHBL, which it generates the control and converts the serial data to parallel data. The proposed system has two test channels and it operates VFCS mode and CFVS mode. The range of test voltage is from 0[V] to 100[V], and the range of test current is from 0[mA] to 100[mA)]. The diode is tested. The test results have a good performance.

• The Journal of Society for e-Business Studies
• /
• v.9 no.1
• /
• pp.21-38
• /
• 2004

With its recent popularity, Web is now considered as a huge repository of information. Most documents on the web have been created using HTML(Hyper Text Markup Language). Even though HTML is simple and easy to learn, it has several features that are obstacles to the efficient information retrieval. XML(eXtensible Markup Language) can provide a solution to such problems and in fact, has already been used in many applications, XML is a standard markup language for exchanging data on the web. It can describe a document structure freely by defining its DTD, which enables efficient integration and retrieval of data on the web. In this paper, we propose a versatile and efficient XML document manager. Its features include (i) form-based XML editor that enables easy creation of new XML documents, (ii) automatic document converter that can transform HTML documents with similar structure into XML documents automatically, and (iii) GUI-based DTD editor.

• The Journal of the Institute of Internet, Broadcasting and Communication
• /
• v.8 no.4
• /
• pp.89-95
• /
• 2008

In the maritime communication, Orthogonal Frequency Division Multiplexing (OFDM) communication terminal should be operated with low power consumption, because the communication should be accomplished in the circumstance of disaster. Therefore, Low power FFT processor is required to be designed with current mode signal processing technique than digital signal processing. Current- to-Voltage Converter (IVC) is a device that converts the output current signal of FFT processor into the voltage signal. In order to lessen the power consumption of OFDM terminal, IVC should be designed with low power design technique and IVC should have wide linear region for avoiding distortion of signal voltage. To design of one-chip of the FFT LSI and IVC, IVC should have a small chip size. In this paper, we proposed the new IVC with wide linear region. We confirmed that the proposed IVC operates linearly within 0.85V to 1.4V as a function of current-mode FFT output range of -100~100[uA]. Designed IVC will contribute to realization of low-power maritime data communication using OFDM system.

• Journal of Advanced Navigation Technology
• /
• v.23 no.6
• /
• pp.561-569
• /
• 2019

Solar photovoltaic can provide electrical energy with only radiation, and its use is expanding rapidly as a new energy source. This study predicts the short and long-term PV power generation using actual converter output data of photovoltaic system. The prediction algorithm uses multiple linear regression, support vector machine (SVM), and deep learning such as deep neural network (DNN) and long short-term memory (LSTM). In addition, three models are used according to the input and output structure of the weather element. Long-term forecasts are made monthly, seasonally and annually, and short-term forecasts are made for 7 days. As a result, the deep learning network is better in prediction accuracy than multiple linear regression and SVM. In addition, LSTM, which is a better model for time series prediction than DNN, is somewhat superior in terms of prediction accuracy. The experiment results according to the input and output structure appear Model 2 has less error than Model 1, and Model 3 has less error than Model 2.

• Journal of the Korea institute for structural maintenance and inspection
• /
• v.18 no.1
• /
• pp.160-165
• /
• 2014

In this study, an efficiency test was performed by fabricating MEMS (Micro Electro Mechanical Systems) based 3-axis acceleration sensor modules and an earthquake monitoring system was composed. Data acquisition device (NI-9239) with a 24bit ADC (Analog to Digital Converter) was used for improving the performance of 3-axis acceleration sensor modules and filtered data (100Hz Low Pass Filter) was used for reducing noises. Also this paper focused on detecting meaningful vibration in the building by developing the earthquake monitoring software. If vector sum of 3-axis acceleration is greater than the preset value, the value will be recorded and saved to the file.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.38C no.7
• /
• pp.623-629
• /
• 2013

This paper presents the implementation result of the EEG(electroencephalogram) signal transmission protocol and its test platform. EEG measured by a dry-type electrode is directly converted into digital signal by ADC(analog-to-digital converter). Thereafter it is transferred DSP(digital signal processor) platform by $I^2C$(inter-integrated circuit) protocol. DSP conducts the pre-processing of EEG and extracts feature vectors of EEG. In this work, we implement the $I^2C$ protocol with 16 channels by using 10 or 12-bit ADC. In the implementation results, the overhead ratio for the 4 bytes data burst transmission measures 2.16 and the total data rates are 345.6 kbps and 414.72 kbps with 10-bit and 12-bit 1 ksps ADC, respectively. Therefore, in order to support a high speed mode of $I^2C$ for 400 kbps, it is required to use 16:1 and $(8:1){\times}2$ ratios for slave:master in 10-bit ADC and 12-bit ADC, respectively.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.21 no.9
• /
• pp.1681-1688
• /
• 2017

In this paper, we implemented a high-speed signal processing hardware system for Color Line Scan Camera using FPGA and Nor-Flash. The existing hardware system mainly processed by high-speed DSP based on software and it was a method of detecting defects mainly by RGB individual logic, however we suggested defect detection hardware using RGB-HSL hardware converter, FIFO, HSL Full-Color Defect Decoder and Image Frame Buffer. The defect detection hardware is composed of hardware look-up table in converting RGB to HSL and 4K HSL Full-Color Defect Decoder with high resolution. In addition, we included an image frame for comprehensive image processing based on two dimensional image by line data accumulation instead of local image processing based on line data. As a result, we can apply the implemented system to the grain sorting machine for the sorting of peanuts effectively.

• Journal of Digital Contents Society
• /
• v.13 no.1
• /
• pp.31-36
• /
• 2012

Since the national standard topographic map is made by DXF format which is the results of the National Geographic Information System project and lots of CAD data and scanners can be used to acquire the data easily, the imports of existing DXF file will decrease the costs and time for data acquisition process. In addition, the spatial data such as topographic map should be able to convert to the middle file format such as PostScript in order to be exported into other systems. For this purpose, I design and implement three units of modules, which are File Manipulation Module, MVF Import Module, and MVF Export Module. Finally, I verify the actual transformation of topographic map that are DXF file format by conducting the series of tests.