• 한국통신학회논문지
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• 제21권11호
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• pp.2850-2861
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• 1996

This paper describes the design of AATM switch LIS of shared buffer type with linked-list architecture to control memory access. The proposed switch LSI consists of the buffer memory, controller and FIFO memory blocks and two special circuits to avoid the cell blocking. One of the special circuit is a new address control scheme with linked-list architecture which maintains the address of buffer memory serially ordered from write address to read address. All of the address is linked as chain is operated like a FIFO. The other is slip-flag register it will be hold the address chain when readaddress missed the reading of data. The circuits control the buffer memory efficiently and reduce the cell loss rate. As a result the designed chip operates at 33ns and occupied on 2.7*2.8mm$^{2}$ using 0.8.mu.m CMOS technology.

• International journal of advanced smart convergence
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• 제1권2호
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• pp.26-29
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• 2012

Recently, to efficiently support the real-time requirements of RTLS( Real Time Location System) services, interest in the main memory DBMS is rising. In the main memory DBMS, because all data can be lost when the system failure happens, the recovery method is very important for the stability of the database. Especially, disk I/O in executing the log and the checkpoint becomes the bottleneck of letting down the total system performance. Therefore, it is urgently necessary to research about the recovery method to reduce disk I/O in the main memory DBMS. Therefore, In this paper, we analyzed existing log techniques and check point techniques and existing main memory DBMSs' recovery techniques for recovery techniques research for main memory DBMS.

• 반도체디스플레이기술학회지
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• 제5권1호
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• pp.17-20
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• 2006

This paper presents of a new type of memory cell that could potentially replace both DRAM and flash memory. The proposed device cell operates by sensing the state of about 1,000 electrons trapped between unique insulating barriers in the channel region of the upper transistor. These electrons are controlled by a side gate on the transistor, and their state in turn controls the gate of the larger transistor, providing signal gain within the memory cell. It becomes faster and more reliable memory with lower operation voltage. Moreover, the use of a multiple tunnel junction (MTJ) fur the vertical transistor can significantly improve the data retention and operation speed.

• IEIE Transactions on Smart Processing and Computing
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• 제5권5호
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• pp.337-345
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• 2016

Recently, as the number of cores in computer systems has increased, the need for larger memory capacity has also increased. Unfortunately, dynamic random access memory (DRAM), popularly used as main memory for decades, now faces a scalability limitation. Phase change memory (PCM) is considered one of the strong alternatives to DRAM due to its advantages, such as high scalability, non-volatility, low idle power, and so on. However, since PCM suffers from short write endurance, direct use of PCM in main memory incurs a significant problem due to its short lifetime. To solve the lifetime limitation, many studies have focused on reducing the number of bit flips per write request. In this paper, we describe the PCM operating principles in detail and explore various bit flip reduction schemes. Also, we compare their performance in terms of bit reduction rate and lifetime improvement.

• 한국생활과학회지
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• 제21권4호
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• pp.705-714
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• 2012

This study investigated the relationships among emotion knowledge, negative emotionality, and autobiographical memory in a sample of 131 three- to five-year-old children attending day care center in seoul. The collected data were analyzed using simple regression and hierarchical multiple regression. The main results of this study were as follows. First, children's emotion knowledge exerted negative effects on their negative emotionality. Second, children's negative emotionality had a positive influence on their autobiographical memory. Finally, the effect of children's emotion knowledge on their autobiographical memory was partially mediated by their negative emotionality. These findings provide a preliminary evidence that children's emotion knowledge and negative emotionality may predict their autobiographical memory.

• 전자공학회논문지B
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• 제29B권10호
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• pp.10-18
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• 1992

This paper considers and implementation of the memory system which provides simultaneous access to pq image points of block(p$\times$q), horizontal vector(1$\times$pq)and/vertical vector(pq$\times$1) in 2-dimension image array, where p and q are design parameters. This memory system consists of an address calculation circuit, address routing circuit, data routing circuit, module selection circuit and m memory modules where m>qp. The address calculation circuit computes pq addresses in parallel by using the difference of addresses among image points. Extra module assignment circuit is not used by improving module selection circuit with routhing circuit. By using Verilog-XL logic simulator, we verify the correctness of the memory system and estimate the performance. The implemented system provides simultaneous access to 16 image points and is 6 times faster than conventional memory system.

• 한국방송∙미디어공학회:학술대회논문집
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• 한국방송공학회 1999년도 KOBA 방송기술 워크샵 KOBA Broadcasting Technology Workshop
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• pp.95-96
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• 1999

The authors have considered the 1/f fluctuation of vial rhythm with $1/f\beta$ spectrum of $\alpha$ wave in relation to the invigoration for the learning memory by paid their attention to the hippocampus protocol in this paper. At the first clinical experiment, the data of the remembrance test at short period is able to make as the foundation of the repeat memory. It can replace this memory with long period memory through the hippocampus by the superposition of the same memory-nerve circuits.

• 센서학회지
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• 제28권4호
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• pp.216-220
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• 2019

In this paper, we propose a finite memory filter (estimator) for discrete-time stochastic linear systems with delays in state and measurement. A novel filtering algorithm is designed based on finite memory strategies, to achieve high estimation accuracy and stability under parametric uncertainties. The new finite memory filter uses a set of recent observations with appropriately chosen initial horizon conditions. The key contribution is the derivation of Lyapunov-like equations for finite memory mean and covariance of system state with an arbitrary number of time delays. A numerical example demonstrates that the proposed algorithm is more robust and accurate than the Kalman filter against dynamic model uncertainties.

• 전자통신동향분석
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• 제37권1호
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• pp.42-52
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• 2022

With the advent of the big data era, the memory capacity required for computing systems is rapidly increasing, especially in High Performance Computing systems. However, the number of DRAMs that can be used in a computing node is limited by the structural limitations of the hardware (for example, CPU specifications). Memory expansion technology has attracted attention as a means of overcoming this limitation. This technology expands the memory capacity by leveraging the external memory connected to the host system through hardware interface such as PCIe and CCIX. In this paper, we present an overview and describe the development trends of the memory expansion technology. We also provide detailed descriptions and use cases of the CCIX that provides higher bandwidth and lower latency than cases of the PCIe.

• 반도체디스플레이기술학회지
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• 제22권3호
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• pp.78-83
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• 2023

This paper proposes a lightweight trace-driven Processing-In-Memory (PIM) simulator, TP-Sim. TP-Sim is a General Purpose PIM (GP-PIM) simulator that evaluates various PIM system performance-related metrics. Based on instruction and memory traces extracted from the Intel Pin tool, TP-Sim can replay trace files for multiple models of PIM architectures to compare its performance. To verify the availability of TP-Sim, we estimated three different system configurations on the STREAM benchmark. Compared to the traditional Host CPU-only systems with conventional memory hierarchy, simple GP-PIM architecture achieved better performance; even the Host CPU has the same number of in-order cores. For further study, we also extend TP-Sim as a part of a heterogeneous system simulator that contains CPU, GPGPU, and PIM as its primary and co-processors.