• Journal of Satellite, Information and Communications
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• v.11 no.3
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• pp.72-79
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• 2016

In this paper, we propose a Service-adaptive Tactical Data Transmission Protocol (STTS) based on Satellite Communications with narrow bandwidth. STTS is designed to provide additional field for scalability and scheduler for reliability of transport stream protocol based on digital broadcasting standard, DVB-S and DVB-S2. It is also verified the effects of lost data packets with narrow bandwidth through the simulator by traffic model and re-transmission of critical data, and checked the design considerations based on STTS system.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.26 no.12
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• pp.1846-1854
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• 2022

The sophistication and diversification of mission equipment for surveillance and reconnaissance is leading to a demand for large-capacity public data links. Overseas, a T4 class(274Mbps) common data link was applied to the Global hwak, a high-altitude unmanned aerial vehicle, and various research and development are being conducted in Korea. In this paper, we propose a structure in which pilot is additionally applied to improve SNR performance while minimizing data transmission rate loss in the DVB-S2 frame structure, which is a european satellite broadcasting standard, for high-capacity transmission of T4 class or higher in the common data link. For the performance evaluation of the proposed structure, the performance of the DVB-S2 was compared and analyzed by simulating the UAV data link channel environment. As a result of simulation, 0.15% of transmission rate loss occurred at T4 class transmission rate compared to DVB-S2 in the proposed structure, but improved SNR reception performance of 0.2~0.3dB was confirmed in the UAV channel environment.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.17 no.3
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• pp.55-61
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• 2017

In DVB-S3 standard of satellite broadcasting systems, FTN technique is applied to LDPC codes with (1+7) PSK modulation. In standard, BICM-ID and BCJR decoding method are considered to alleviate performance degradation due to FTN processing. BICM-ID method improves performance by calculating a new LLR from hard-decision value of decoder output. BCJR also improves performance by calculating forward and backward matrix each other. However these two methods require high computational complexity. Therefore this paper proposed modified decoding method in order to reduce computational complexity without performance degradation.

• Journal of Satellite, Information and Communications
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• v.10 no.3
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• pp.62-67
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• 2015

This paper we introduce next-generation VSAT system based on DVB-RCS2 which is second-generation satellite communication standard. We construct a test-bed for the functional verification of return link modem and discuss the results. According to this, we expect to efficient use of technology for the next-generation VSAT services and broadcasting services.

• Electronics and Telecommunications Trends
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• v.33 no.3
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• pp.34-40
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• 2018

Current studies based on the DVB-S2x standard for the next-generation multi-beam HTS/BH satellite have been investigated. To enhance the efficiency of the transmission throughput and maximize the utilization of the satellite payload resources and bandwidth, the concepts of two advanced techniques, namely, precoding and BH, are described. Furthermore, state-of-the-art aspects currently under discussion, and future study items in the DVB TM-S standardization group, are summarized in this article.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.06a
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• pp.185-185
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• 2008

This paper describes the broadband SDC (Single-ended to Differential Converter) for Digital Video Broadcasting-Satellite $2^{nd}$ edition (DVB-S2) receiver tuner IC. It is fabricated by using $0.18{\mu}m$ CMOS process. In order to obtain high linearity and low phase mismatch, the broadband SDC (Single-ended to Differential Converter) is designed with current mirror structure and cross-coupled capacitor and current source binding differential structure at VDD. The simulation result of SDC shows IIP3 of 11.9 dBm and IIP2 of 38 dBm. It consumes 5mA current with 2.7V supply voltage.

• Journal of Satellite, Information and Communications
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• v.9 no.2
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• pp.23-27
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• 2014

In this paper, we propose a soft demapping method for 64-ary APSK in the DVB-S3 system. The proposed method in this paper uses the hard decision threshold (HDT) line for each constituent bit in a symbol, and calculates the soft bit information with the distance between the HDT line and the detected symbol. If the HDT lines are defined in a simple manner, the complexity to estimate soft information can be largely reduced compared with the maximum likelihood detection (MLD) which has an exponential complexity. By considering this, we first derive HDT lines for each constituent bit for a 64-APSK symbol, and propose a method to calculate soft bit information. We simulate the BER performance of the proposed scheme by using a turbo codes which requires soft-input-soft-output information, and compare it that of the MLD. The result show that the proposed scheme produces approximating performance to MLD with largely reduced complexity.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.38C no.3
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• pp.311-317
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• 2013

In this paper, we proposed high speed LDPC decoding algorithm based on DVB-S2 standard for applying marine communications in order to multimedia transmission. For implementing the high speed LDPC decoder, HSS algorithm which reduce the iteration numbers without performance degradation is applied. In HSS algorithm, check node update units are update at the same time of bit node update. HSS can be accelerated to the decoding speed because it does not need to separate calculation of the bit nodes, However, check node calculation blocks need many clocks because of just one memory is used. Therefore, this paper proposed partial memory structure in order to reduced the delay and high speed decoder is possible. The results of the simulation, when the max number of iteration set to 30 times, decoding throughput of HSS algorithm is 326 Mbit/s and decoding speed of proposed algorithm is 2.29 Gbit/s. So, decoding speed of proposed algorithm more than 7 times could be obtained compared to the HSS algorithm.

• Journal of Satellite, Information and Communications
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• v.8 no.4
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• pp.75-80
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• 2013

In this paper, the Ka-band maritime satellite communication systems for mobile terminals are proposed. The design includes the link budget analysis, determination of modulation and coding schemes and the overall structure of a transmitter. To avoid the harmful effects on the existing DVB-S2 services, the proposed maritime satellite system using the same spectrum with DVB-S2 at the same time employs the very wideband spreading transmission. Additionally, omni-directional low-gain antennas should be equipped in a mobile terminal to reduce the system cost. These two considerations limit the maximum transmission rate of the proposed system. Due to the limitations, the proposed system includes 36 dB or 39 dB spreading gain depending on the modulation scheme and a link-adaptive repetition method depending on the level of rain attenuation. To support short packets with minimal performance loss, the turbo code used in 3GPP instead of LDPC(low density parity check code) is adopted. By combining them, the overall structure of low-rate maritime satellite communication system is designed.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.34 no.3A
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• pp.265-271
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• 2009

This paper proposes an efficient initial frequency estimator for Digital Video Broadcasting-Second Generation (DVB-S2). The initial frequency offset of the DVB-S2 is around ${\pm}5MHz$, which corresponds to 20% of the symbol rate at 25Msps. To estimate a large initial frequency offset, the algorithm which call provide a large estimation range is required. Through the analysis of the data-aided (DA) algorithms, we find that the Mengali and Moreli (M&M) algorithm can estimate a large initial frequency offset at low SNR. Since the existing frequency estimator based on M&M algorithm has a high hardware complexity, we propose the methods to reduce the hardware complexity of the initial frequency estimator. This can be achieved by reducing the number of autocorrelators and arctangents. The proposed architecture can reduce the hardware complexity about 64.5% compared to the existing frequency estimator and has been thoroughly verified on the Xilinx Virtex II FPGA board.