• Journal of Satellite, Information and Communications
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• v.3 no.2
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• pp.38-42
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• 2008

In 2005, DVB-S2 spec. was finalized. But with a large number of DVB-S receivers already installed, backwards compatibility may be required for a period of time, where old receivers continue to receive the same capacity as before, while the new DVB-S2 receivers could receive additional capacity broadcasts. To facilitate the reception of DVB-S serviced by DVB-S2 receivers, implementation of DVB-S in DVB-S2 chips is highly recommended. For the backward compatibility the system adapt the hierarchical modulation scheme. And the system has to meet system margin, so in this paper analyzes the effect according to the deviation angle and shows the BER performance. And finally this paper shows the result of the system implement using FPGA chip.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.40 no.11
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• pp.2113-2120
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• 2015

This paper presents an integrated receiver to support multimode broadcasting standards such as DVB-T2, DVB-C2, and DVB-S2 in a single platform. The integrated receiver consists of a tuner block, a receiver engine, a frame processor, and an A/V decoder. The receiver engine includes a channel decoding engine and a demodulation engine to perform OFDM and APSK demodulations. The frame processor performs deinterleaving and BB frame decoding functions. The demodulator engine and the frame processor are implemented in two FPGA devices and DSP-based embedded software, respectively. To verify the functionality of the integrated receiver, it is tested in the laboratory. Commercial PC-based modulators are used to generate the DVB-T2, DVB-C2, and DVB-S2 modulated signals. The integrated receiver was tested under various operation modes as specified in the standards such as DVB-T2, DVB-C2, and DVB-S2 and showed successful operation in all the scenarios tested.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2004.11a
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• pp.185-191
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• 2004

이 연구는 DVB-S2 BC(Backward Compatibility) 모드에서 대역폭 효율을 개선하기 위한 새로운 계층적 변조방식을 제안하였다. DVB-S2 표준은 기존 DVB-S 방송 서비스와의 역호환성을 위하여 비대칭 8-PSK를 사용하며, 이 방식은 DVB-S의 경우보다는 대역폭 효율이 개선되나 DVB-S2 NBC(Non Backward Compatibility) 모드보다는 개선도가 미약하다 이러한 문제점을 해결하기 위하여 DVB-S2 NBC에서 사용하는 16APSK 변조방식을 DVB-S2 BC 모드에서 사용할 수 있도록 변형하였으며, 변형된 16-APSK 방식에 대한 수신 성능을 통계적 방법을 통하여 분석하였다.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.19 no.10
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• pp.1075-1085
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• 2008

Recently, it is studied actively that DVB-S2 for mobility standard(DVB-S2M) is combined with DVB-H, DVB-T and conventional DVB-S2 standard for continuous satellite broadcasting and internet service. Especially, overcoming deep fading by tunnel is main subject. For overcoming deep fading, DVB-S2M proposed cross layer system is consist of upper layer and physical layer. Thus, this paper proposed optimal upper layer coding system fixing the physical layer coding under the simulation results by coding methods, train speed, data rate, interleaver size and IP packet size.

• Proceedings of the KIEE Conference
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• 2007.07a
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• pp.1872-1873
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• 2007

최근 유럽에서는 사용자와 운영자들의 요구에 부응하여 기존 DVB 위성 광대역 서비스에 대한 표준을 DVB-S에서 DVB-S2로 업그레이드 시켰다. DVB-S2는 ACM을 적용하여 여러 채널환경에서 기존의 표준보다 안정적인 전송과 높은 효율을 보여준다. DVB-S2 시스템은 FEC 알고리듬으로써 LDPC와 BCH를 사용하고 있다. LDPC는 R. G. Gallager에 의해 고안된 블록부호화 방식으로 검사행렬 H에서 1의 sparse 한 성질을 이용하여 큰 블록에서 더 좋은 성능을 발휘하도록 되어있다. 본 논문에서는 DVB-S2의 중요 서브시스템인 FEC블록 중 LDPC 복호기에 관하여 ACM을 적용하여 상위수준 시뮬레이션을 실시하였다. 실험결과 각 변조 방식 및 부호율에 따라서 BER이 SNR 0에서 14dB까지 넓게 분포함을 확인하였다. 그러므로 채널 환경에 따라 변조방식과 부호율을 달리하여 속도를 향상시키거나 데이터의 안정성을 높일 수 있다. 그리고 이 때 LDPC 복호기가 충분히 성능을 발휘함을 알 수 있다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.9 s.351
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• pp.31-37
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• 2006

Low-density parity-check (LDPC) codes are recently emerged due to its excellent performance. The standard for European high definition satellite digital video broadcast, DVB-S2 has adopted LDPC codes as a channel coding scheme. This paper proposes a DVB-S2 LDPC decoder architecture using a hybrid parity check matrix which is efficient in hardware implementation for both decoders and encoders. The hybrid H-matrices are constructed so that both the semi-random technique and the partly parallel structure can be applied to design encoders and decoders. Using the hybrid H-matrix scheme, the architecture of LDPC decoder for DVB-S2 can be very practical and efficient. In addition, we show a new Variable Node processor Unit (VNU) architecture to reuse the VNU for various code rates and optimized block memory placement to reuse. We design a DVB-S2 LDPC decoder of code rate 1/2 usng the proposed architecture. We estimate the performance of the DVB-S2 LDPC decoder and compare it with other decoders.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2009.11a
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• pp.91-94
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• 2009

현재 여러 나라에서 유럽의 위성 전송 시스템인 DVB-S 표준을 적용한 위성방송이 실시되고 있다. 또한 HDTV와 같은 광대역 방송 서비스, 인터넷 서비스 제공을 위한 효율적인 위성링크 등의 필요성으로 인해 2세대 위성방송 표준인 DVB-S2 (Digital Video Broadcasting via stellite) 표준이 제정되었다. DVB-S2 수신기의 반송파 동기부는 대부분의 상용 DVB-S2 수신기에 사용되는 상용 부품으로 인한 상당히 큰 초기 반송파 주파수 오차(심볼속도 대비 20%)를 정확하게 추정하고 복구해야만 한다. 이런 이유로, 기존의 DVB-S2 수신기의 반송파 주파수 복구부는 많은 연산량을 필요로 하고 복잡한 하드웨어 구조를 가진다. 이에 본 논문에서는 기존의 반송파 주파수 복구부에 비해 성능의 열화가 없고, 간단한 구조를 가지는 견고한 반송파 주파수 복구부 방식을 제안하였다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.34 no.5C
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• pp.485-497
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• 2009

In this paper, we described DVB-S2 system for mobility. cross layer coding technique are needed to maintain the performance in deep fading channel. Cross layer coding is divided into two kinds of level. First level is Physical layer coding and, second layer is link layer or upper layer coding. Fixed on DVB-S2 short frame coding method as a physical layer, we simulated the various coding method as an upper layer coding. Furthermore, we analyzed the performance of each coding method on according to mobile vehicle speed, data rate, interleaving memory size, and IP packet size.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.11C
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• pp.901-906
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• 2010

Low density parity check (LDPC) code, first introduced by Gallager and re-discovered by MacKay et al, has attracted researcher's interest mainly due to their performance and low decoding complexity. It was remarkable that the performance is very close to Shannon capacity limit under the assumption of having long codeword length and iterative decoder. However, comparing to turbo codes widely used in the current mobile communication, the encoding complexity of LDPC codes has been regarded as the drawback. This paper proposes a solution for DVB-S2 LDPC encoder to reduce the encoder latency. We use the fast IRA encoder that use the transformation of the parity check matrix into block-wise form and the partial parallel process to reduce the number of system clocks for the IRA code encoding. We compare the proposed encoder with the current DVB-S2 encoder to show that the performance of proposal is better than that of the current DVB-S2 encoder.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.4A
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• pp.371-376
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• 2010

This paper presents an efficient demapper architecture based soft-decision using the phase-section for Digital Video Broadcasting via satellite, Second Generation (DVB-S2). To achieve the satisfactory performance under a very low SNR conditions with the efficient hardware resource utilization, we propose a simple soft-decision demapper architecture using comparators to compare the phase of symbols and memories. The proposed architecture can decrease about 81% of the hardware resource, satisfying the BER requirements of DVB-S2. It has been thoroughly verified with an FPGA board and R&S(R)SFU (Rohde&Schwarz SFU-K108) broadcaast test equipment.