• Proceedings of the KIEE Conference
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• 2006.04a
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• pp.255-257
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• 2006

This paper proposed a platform which includes both Network processor and DSP for flexible IED. The Network processor is one of the Intel's IXP4XX Product Line family and the DSP is one of the TI's C6000 family. An embedded Linux is ported in Network processor so that a DSP program can be downloaded to Network processor through ethernet and then downloaded to DSP. Using this method, various algorithms according to IED can be applied to the Network processor board. Maximum ten ADCs can be connected because there is a CPLD between DSP and ADC. That is, the network processor board which can measure maximum 40 channels is implemented. In DSP program, thread and double buffering methods are used not to miss voltage samples. The Network processor board is verified using a method that eight channel voltage signals converted to digital are transmitted to server through both DSP and IXP425.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.20 no.2
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• pp.141-147
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• 2020

We studied for GPU based signal processor for naval multi-function radar. We implemented processing software both DSP and GPU, and compared computation performances and power consumption. As a result, computation performance was enhanced from 1.2 to 4.1 times compared with a DSP result. From the results, GPU can alternating DSP based signal processor for common radar processor even though Naval Multi Function Radar.

• Journal of IKEEE
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• v.26 no.2
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• pp.280-286
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• 2022

This paper presents implementation of rapid control prototype (RCP) for permanent magnet synchronous machines (PMSMs) using a digital signal processor (DSP) and the PLECS software. By utilization of auto code generation function in the PLECS, a current vector control algorithm for a PMSM drive system using a DSP as a control processor can be developed more efficiently. In this paper, a background of a model based design (MBD) and real time control are reviewed. Also, commercial RCP products compatible with DSP boards are introduced. At the end of the paper, experimental implementation of RCP for a PMSM drive is presented.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.8 no.4
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• pp.833-837
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• 2004

The iris image recognition system realization using DSP processor for the faster real-time processing is presented in this paper. The system is composed of CCD camera, DSP processing and network part to link the communication. The system based on high speed DSP processor leads the iris recognition processing time to be faster. The simulation results in 0.9sec below approximately.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2003.10a
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• pp.264-267
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• 2003

The stereoscopic vision robot system design with DSP processor is presented. The vision system is consists of control system, vision system and host computer. The vision system is based on 32bits DSP processor. The stereoscopic image processing applies the correlation coefficient method to execute the software. The result of experiment, image recognition rate is 95% on the stereoscopic vision robot system.

• 제어로봇시스템학회:학술대회논문집
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• 1990.10b
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• pp.923-928
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• 1990

This paper describes the design and implementation of a real-time, high-precision vision system and its application to SMT(surface mounting technology) automation. The vision system employs a 32 bit MC68030 as a main processor, and consists of image acquisition unit. DSP56001 DSP based vision processor, and several algorithmically dedicated hardware modules. The image acquisition unit provides 512*480*8 bit image for high-precision vision tasks. The DSP vision processor and hardware modules, such as histogram extractor and feature extractor, are designed for a real-time excution of vision algorithms. Especially, the implementation of multi-processing architecture based on DSP vision processors allows us to employ more sophisticated and flexible vision algorithms for real-time operation. The developed vision system is combined with an Adept Robot system to form a complete SMD system. It has been found that the vision guided SMD assembly system is able to provide a satisfactory performance for SND automation.

• Journal of Korea Society of Digital Industry and Information Management
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• v.15 no.4
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• pp.93-101
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• 2019

This paper presents a software design and implementation of software-defined radio based IEEE 802.11ac encoder using Texas Instruments TMS320C6670 digital signal processor (DSP) platform. In this paper, the implemented encoder has the capability of generating all the signals consisting of preamble field and data field under different modulation & coding scheme in the IEEE 802.11ac standard. Moreover, the flexibility in choosing different rate, bandwidth, or mode can also be achieved by software reconfiguration using the DSP. As a result, by utilizing the computing power provided by multi-cores as well as the FFT coprocessors in the DSP, the required maximum throughput 78Mbps can be fully reached within 4 ㎲ for each OFDM symbol in the case of 20MHz bandwidth of IEEE 802.11ac.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.12C
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• pp.1617-1622
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• 2004

MPEG/Audio decoder for mobile multimedia systems requires low power consumption. Implementations of AV decoder using a single RISC processor often need high power consumption owing to cash-miss in case of insufficient cash memory. In this paper, we present a MPEG/Audio decoder for mobile handset applications and implement it on a RISC processor embedding a minimized DSP accelerator. Audio decoding algorithm is splined into two parts; computation intensive and control intensive parts. Those parts we, respectively, allocated to DSP and RISC core, which are designed to run in parallel to increase the processing efficiency. The proposed system implements MP3 and AAC decoders at l7MHz and 24MHz clocks, which are reductions of 48% and 40% of complexities in comparison with implementations on a single RISC processor. The proposed method is adequate for mobile multimedia applications with insufficient cash memory.

• 제어로봇시스템학회:학술대회논문집
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• 1993.10a
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• pp.685-691
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• 1993

This paper introduces a PC-based image data processing unit that is composed of preprocessor board and main processor board; The preprocessor contains Inmos A110 processor and efficient H/W architecture for fast mask/logic operations at the speed of video signal rate. It is controlled by the main processor which communicates with the host PC. The main processor board contains TI TMS320C31 digital signal processor, and can access the frame memory of the processor for extra S/W tasks. We test 3*3, 5*5 masks and logic operations on 386/486/DSP and compare the result with that of the proposed unit. The result shows ours are extremely faster than conventional CPU based approach, that is, over several hundred times faster than even DSP.

• Proceedings of the Korea Electromagnetic Engineering Society Conference
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• 2005.11a
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• pp.23-28
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• 2005

An airborne radar is an essential aviation electronic system of the helicopter to perform various missions in all-weather environments. This paper presents the results of the design and implementation of the airborne pulse doppler radar signal processor using high multi-DSP for the multi-function radar capability such as short-range, midium-range, and long-range depending on the mission of the vehicle. Particularly, the radar signal processor is developed using two DSP boards in parallel for the various radar signal processing algorithm. The key algorithms include LFM chirp waveform-based pulse compression, MTI clutter filter, MTD processor, adaptive CFAR, and clutter map. Especially airborne moving clutter Doppler spectrum compensation algorithm such as TACCAR is implemented for the multi-mode airborne radar system. The test results shows the good Doppler spectral separation for the clutter and the moving target in the flight test environment using helicopter.