• Journal of Institute of Control, Robotics and Systems
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• v.12 no.6
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• pp.530-538
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• 2006

DSP chip parameters of a digital hearing aid (HA) should be optimally selected or fitted for hearing impaired persons. The more precise parameter fitting guarantees the better compensation of the hearing loss (HL). Digital HAs adopt DSP chips for more precise fitting of various HL threshold curve patterns. A specific DSP chip such as Gennum GB3211 was designed and manufactured in order to match up to about 4.7 billion different possible HL cases with combination of 7 limited parameters. This paper deals with a digital HA fitting program which is developed for optimal fitting of GB3211 DSP chip parameters. The fitting program has completed features from audiogram input to DSP chip interface. The compensation effects of the microphone and the receiver are also included. The paper shows some application examples.

• 제어로봇시스템학회:학술대회논문집
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• 2005.06a
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• pp.1820-1825
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• 2005

DSP chip parameters of a digital hearing aid (HA) should be optimally selected or fitted for hearing impaired persons. The more precise parameter fitting guarantees the better compensation of the hearing loss (HL). Digital HAs adopt DSP chips for more precise fitting of various HL threshold curve patterns. A specific DSP chip such as Gennum GB3211 was designed and manufactured in order to match up to about 4.7 billion different possible HL cases with combination of 7 limited parameters. This paper deals with a digital HA fitting program which is developed for optimal fitting of GB3211 DSP chip parameters. The fitting program has completed features from audiogram input to DSP chip interface. The compensation effects of the microphone and the receiver are also included. The paper shows some application examples.

• ETRI Journal
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• v.19 no.3
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• pp.228-241
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• 1997

In this paper, we present a design of modem and vocoder digital signal processor (DSP) chips for CDMA mobile station. The modem chip integrates CDMA reverse link modulator, CDMA forward link demodulator and Viterbi decoder. This chip contains 89,000 gates and 29 kbit RAMs, and the chip size is $10 mm{\times}10.1 mm$ which is fabricated using a $0.8{\mu}m$ 2 metal CMOs technology. To carry out the system-level simulation, models of the base station modulator, the fading channel, the automatic gain control loop, and the microcontroller were developed and interfaced with a gate-level description of the modem application specific integrated circuit (ASIC). The Modem chip is now successfully working in the real CDMA mobile station on its first fab-out. A new DSP architecture was designed to implement the Qualcomm code exited linear prediction (QCELP) vocoder algorithm in an efficient way. The 16 bit vocoder DSP chip has an architecture which supports direct and immediate addressing modes in one instruction cycle, combined with a RISC-type instruction set. This turns out to be effective for the implementation of vocoder algorithm in terms of performance and power consumption. The implementation of QCELP algorithm in our DSP requires only 28 million instruction per second (MIPS) of computation and 290 mW of power consumption. The DSP chip contains 32,000 gates, 32K ($2k{\times}16\;bit$) RAM, and 240k ($10k{\times}24\;bit$) ROM. The die size is $8.7\;mm{\times}8.3\;mm$ and chip is fabricated using $0.8\;{\mu}m$ CMOS technology.

• Proceedings of the IEEK Conference
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• 2005.11a
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• pp.415-418
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• 2005

DSP chip parameters of a digital hearing aid (HA) should be optimally selected or fitted for hearing impaired persons. The more precise parameter fitting guarantees the better compensation of the hearing loss (HL). Digital HAs adopt DSP chips for more precise fitting of various HL threshold curve patterns. A specific DSP chip such as Gennum GB3211 was designed and manufactured in order to match up to about 4.7 billion different possible HL cases with combination of 7 limited parameters. This paper deals with a digital HA fitting program which is developed for optimal fitting of GB3211 DSP chip parameters. The fitting program has completed feature from audiogram input to DSP chip interface. The compensation effects of the microphone and the receiver are also included. The paper shows some application examples.

• 제어로봇시스템학회:학술대회논문집
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• 2005.06a
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• pp.190-195
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• 2005

The hearing aid chip described in this paper is an analog & digital mixed system. The design focuses on the$\mu$DSP core. This $\mu$DSP core includes internal time delays to two inputs from front and rear microphones. The paper consists of two parts; one is the composure and signal processing algorithm of digital hearing aids and the other is Verilog HDL codes for$\mu$DSP cores. All digital modules in the design were coded and synthesized by Verilog HDL codes which were verified by Mentor Graphics and Synopsis semiconductor chip design tools.

• Proceedings of the Acoustical Society of Korea Conference
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• 1994.06a
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• pp.957-962
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• 1994

Real-time RELP vocoder is implemented on the TMS320C25 DSP chip. The implemented system is IBM-PC add-on board and composed of analog in/out unit, DSP unit, memoy unit, IBM-PC interface unit and its supporting assembly software. Speech analyzer and synthesizer is implimented by DSP assembly software. Speech parameters such as LPC coefficients, base-band residuals, and signal gains is extracted by autocorrelation method and inverse filter and synthesized by spectral folding method and direct form synthesis filter in this board. And then, real-time RELP vocoder with 9.6Kbps is simulated by down-loading method in the DSP program RAM.

• Speech Sciences
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• v.14 no.4
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• pp.157-167
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• 2007

In this paper, we implemented a single-chip speech recognizer using the TMS320C2000 DSPs. For this implementation, we had developed very small-sized speaker-dependent recognition engine based on dynamic time warping, which is especially suited for embedded systems where the system resources are severely limited. We carried out some optimizations including speed optimization by programming time-critical functions in assembly language, and code size optimization and effective memory allocation. For the TMS320F2801 DSP which has 12Kbyte SRAM and 32Kbyte flash ROM, the recognizer developed can recognize 10 commands. For the TMS320F2808 DSP which has 36Kbyte SRAM and 128Kbyte flash ROM, it has additional capability of outputting the speech sound corresponding to the recognition result. The speech sounds for response, which are captured when the user trains commands, are encoded using ADPCM and saved on flash ROM. The single-chip recognizer needs few parts except for a DSP itself and an OP amp for amplifying microphone output and anti-aliasing. Therefore, this recognizer may play a similar role to dedicated speech recognition chips.

• Proceedings of the KIEE Conference
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• 1996.07b
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• pp.1295-1297
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• 1996

CCITT G.721, G.723 standard ADPCM algorithm is implemented by using TI's fixed point DSP start kit (DSK). ADPCM can be implemented on a various rates, such as 16K, 24K, 32K and 40K. The ADPCM is sample based compression technique and its complexity is not so high as the other speech compression techniques such as CELP, VSELP and GSM, etc. ADPCM is widely applicable to most of the low cost speech compression application and they are tapeless answering machine, simultaneous voice and fax modem, digital phone, etc. TMS320C50 DSP is a low cost fixed point DSP chip and C50 DSK system has an AIC (analog interface chip) which operates as a single chip A/D and D/A converter with 14 bit resolution, C50 DSP chip with on-chip memory of 10K and RS232C interface module. ADPCM C code is compiled by TI C50 C-compiler and implemented on the DSK on-chip memory. Speech signal input is converted into 14 bit linear PCM data and encoded into ADPCM data and the data is sent to PC through RS232C. The ADPCM data on PC is received by the DSK through RS232C and then decoded to generate the 14 bit linear PCM data and converted into the speech signal. The DSK system has audio in/out jack and we can input and out the speech signal.

• 제어로봇시스템학회:학술대회논문집
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• 1991.10a
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• pp.292-298
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• 1991

A new 6-axis robot controller with a high-speed 32-bit floating-point DSP TMS32OC30 has been developed in Samsung Electronics. The controller composed of Intel 80386 microprocessor for the main controller, and TKS32OC30 DSP chip for joint position controller. The characteristics of the controller are high sampling rate of 200us and fast reponsibility. The main controller supports MS-DOS, kinematics, trajectory planning, and sensor fusion functions which are vision, PLC, and MAP. The one high speed DSP chip is used for controlling 6 axes of a robot in 200us simultaneously. The control law applied is PID controller including a velocity feedforvard in joint position controller. The performance tests, such as command following, CP, were conducted for the controller integrated with a 6 axes robot developed in Samsung Electronics. The results showed a good performance. This controller can also perform the system control with other controllers, the communication with high priority controllers, and visual information processing.

• Proceedings of the Acoustical Society of Korea Conference
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• 1998.08a
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• pp.165-168
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• 1998

제안하고 있는 CSD17C00 chip은 C&S technology에서 개발한 것으로, 음성 신호 처리를 위해 범용으로 구현되었으며, 16 bit 40 MIPS DSP group OAK DSP Core를 포함, 이에 Miscellaneous Logic, Serial Port, Host Interface, Timer, Compander 의 5가지 Peripherals 과 범용 I/O Ports 로 설계되었다. 1차적으로 CSD17C00 Chip 의 성능을 점검하였다. 그 결과, 응용 프로그램은 28MIPS의 계산속도를 갖으며, 프로그램 ROM 크기는 8.85KWords 이고, 10KWords 의 데이터 ROM 과 4KWords 데이터 RAM을 필요로 한다. CSD17C00 CHIP은 멀티미디어 통신용 VOCODER 개발을 위한 범용성을 갖추고 있으며, VOCODER 용 S/W 개발 환경 및 H/W 구조가 여타 범용 DSP에 비해편의성고 K합리성을 제공하도록 설계되어 있다. 따라서, 이를 이용한다면, 멀티 미디어 통신용 VOCODER, INTERNET PHONE CO-PROCESSOR, DIGITAL RECODER, MPEG AUDIO ENCODER & DECODER 등 다양한 제품으로의 응용이 가능할 것으로 전망된다.