• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.4C
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• pp.388-397
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• 2002

We designed a SIMD-DSP/FPU that can efficiently improve multimedia processing performance when integrated into high-performance embedded microprocessors. We proposed partitioned architectures and new schemes for several functional units to reduce chip area. Sharing functional units reduces the area of FPU significantly. The proposed architecture is modeled in HDL and synthesized with a 0.35$\mu\textrm{m}$ standard cell library. The chip area is estimated to be about 100,000 equivalent gates. The designed unit can run at higher than 50MHz clock frequency of CPU core under the worst-case operating conditions.

• Proceedings of the Acoustical Society of Korea Conference
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• spring
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• pp.339-342
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• 2000

본 논문에서는 DSP와 RISC 마이크로 콘트롤러의 결합으로 구성된 이중 코어 DSP를 이용하여 휴대장치에 적합한 저전력 MPEC-2 계층-III 복호화기의 구조를 제안하고 실시간 시스템을 구현하였다. 제안된 시스템은 디지털 오디오 데이터 처리부와 시스템 제어 정보처리부로 나누어 병렬처리가 가능한 구조이다. 디지털 오디오데이터 처리부에서는 DSP의 강력한 산술연산기능으로 MPEG 복호화 알고리듬을 수행하며 시스템 제어부에서는 마이크로 콘트롤러의 장점인 저가, 저전력의 제어 기능으로 사용자 인터페이스 및 파일 관리, 비트스트림 제어를 담당하도록 구성된다. 입력부에서는 Multi Meadia Card(MMC)를 지원하고, PC와 호환 가능하도록 파일 관리 시스템으로 운용되며 직렬 통신의 데이터 전송과 16비트 해상도 및 최대 48kHz 표본화주파수로 스테레오 출력이 가능하다. 구현된 시스템은 이중 코어를 이용하여 DSP의 연산량 및 동작속도의 감소로 인한 저가, 저전력의 효과로 인해 휴대장치에 적합하다.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.39 no.1
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• pp.63-68
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• 2011

Many countries all over the world have been doing lunar exploration projects. Korea has also been doing basic research on lunar exploration. The development of communication systems for lunar exploration projects is one of the most important aspects of performing a successful lunar mission. In this paper, we design a DSP (Digital Signal Processor) prototype based on the requirement analysis of a communication link for lunar exploration and implement its core module considering the international standards for deep space communications to perform a basic research on baseband processor development. It is verified by comparing the bit error rate of the DSP prototype with that of a computer simulation.

• Korean System Dynamics Review
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• v.4 no.2
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• pp.5-44
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• 2003

The focus of this paper is comparing relative effects of government policies for upbringing information security industry from the dynamic point of view. For the purpose of simplicity, these policies are classified into three groups, and then the relative effectiveness of these policy groups is examined using System Dynamics. The three policy groups are composed of technology development policies (TDP), human resource development policies (HDP), and direct supporting policies for overseas expansion (DSP). From the result of the analysis, DSP appears to be the most effective and HDP is the second-best group. By the way, for successful carrying into effect of DSP, marketing manpower should be strengthen. However, current HDP has been focusing on the bringing up technical experts. Therefore, overseas marketing manpower should be reared as well as technicians. Also, the existing infrastructure for overseas expansion for other industries should be shared for DSP of information security industry, because this is essential for success of DSP in terms of timing and costing. Finally, in spite of its low effect, TDP should be maintained continuously. The importance of information security technology is increasing and some countries have already considered these technologies as a core of future national defense. Therefore, we should acquire the competitiveness for a few technologies through continuous development of selected technologies at least.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.49 no.1
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• pp.119-127
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• 2012

This paper describes development and performance test of signal processor for the millimeter wave seeker. A ground to air guidance missile is required various beam patterns in order to counteract different kind of target. Therefore, we designed the hardware and software architecture considering flexibility. This signal processor consists of ADC, FPGA, DSP and etc. FPGA provides peripheral interface to DSP and convert digital IF signal to baseband signal. DSP performs signal processing, calculates target's information and controls devices. Each parts' hardware are connected in series and signal processing algorithms for various beam patterns are built in parallel.

• Proceedings of the IEEK Conference
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• 2003.07d
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• pp.1395-1398
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• 2003

This paper presents a 32-bit RISC Micro-Controller which is useful in the dedicated DSP and communication areas. The designed processor has 5 stages pipeline architecture, and 28 instructions. This RISC Micro-Controller consist of 22,100 gates and has 5.95 ns data arrival time, and 437 ㎽ total dynamic power. The RISC Micro-Controller is a IP (Intellectual property) Core module which can implement a number of protocols by and is applicable to DSP and data communication.

• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.1123-1126
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• 1999

In this paper, we propose a real-time implementation of the MPEG-1 layer III and MPEG-2 layer III LSF audio decoding system based on OAK DSP Core. In order to solve the problem of resolution, the system has been used floating-point operation and double precision in dequantization module. The size of ROM is reduced by using the Run-length algorithm of reordered index. The subband synthesis filter module is optimized to have low computational complexity in terms of the size of ROM or RAM. To construct a efficient system, we used both the DSP Core and Parser-Huffman decoder which is implemented with VHDL.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.23 no.6
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• pp.1433-1442
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• 1998

The thesis presents a dual audio decoder which can decode both AC-3 and MPEG-2 bitstream. The MPEG-2 synthesis processi s optimized via FFT to establish the common data path with AC-'3s. A dual audio decoder consists of a DSP core which performs the control-intensive part of each algorithm and a common synthesis filter which perfomrs the computation-intensive part. All the components of the dual audio decoder have been described in VHDL and simulated with a SYNOPSYS tool. The software modeling of the DSP core was used for functional validation. After being synthesized using 0.6 .mu.m-3ML technology standard cell, the dual audio decoder was simulated at gate-level with a COMPASS tool for hardware validation.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2016.05a
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• pp.683-684
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• 2016

The up-to-date high-performance DSP or FPGA employs SRIO(Serial Rapid IO) as a high-speed serial communications. SRIO is an industry standard regulated upto Ver 3.1. In this study we developed a backplane having a transmission rate to 15Gbps based on a TI DSP. The back plane icould be used to High-speed video transmission, and will be adopted to connecting multiple DSPs for scalable architecture. This paper will discuss the design constraints for a high-speed communication and multiple-core operation.

• Journal of Korea Society of Digital Industry and Information Management
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• v.14 no.4
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• pp.79-85
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• 2018

This paper presents an implementation method of Long Term Evolution-Advanced (LTE-A) Physical Downlink Shared Channel (PDSCH) decoder using a general-purpose multicore Digital Signal Processor (DSP), TMS320C6670. Although the DSP provides some useful coprocessors such as turbo decoder, fast Fourier transformer, Viterbi Coprocessor, Bit Rate Coprocessor etc., it is specific to the base station platform implementation not the mobile terminal platform implementation. This paper shows an implementation method of the LTE-A PDSCH decoder using programmable DSP cores as well as the coprocessors of Fast Fourier Transformer and turbo decoder. First, it uses the coprocessor supported by the TMS320C6670, which can be used for PDSCH implementation. Second, we propose a core programming method using DSP optimization method for block diagram of PDSCH that can not use coprocessor. Through the implementation, we have verified a real-time decoding feasibility for the LTE-A downlink physical channel using test vectors which have been generated from LTE-A Reference Measurement Channel (RMC) Waveform R.6.