• Proceedings of the KIPE Conference
• /
• 2012.07a
• /
• pp.315-316
• /
• 2012

Three-level neutral point clamping (NPC) converter has been widely applied in high power drive system. And in this paper, a novel method is proposed to realize this algorithm based on FPGA, And the system is consist of two parts, the DSP part and FPGA part, the DSP part includes the control algorithms and the FPGA part works to generate and putout 12 PWM pulses. And the system is tested and verified using both simulation and experimentation.

• The Transactions of the Korean Institute of Electrical Engineers A
• /
• v.48 no.12
• /
• pp.1554-1563
• /
• 1999

This paper presents the design of high speed processor for a sequence logic control using field programmable gate array(FPGA). The sequence logic controller is widely used for automating a variety of industrial plants. The FPGA designed by VHDL consists of program and data memory interface block, input and output block, instruction fetch and decoder block, register and ALU block, program counter block, debug control block respectively. Dedicated clock inputs in the FPGA were used for high speed execution, and also the program memory was separated from the data memory for high speed execution of the sequence instructions at 40 MHz clock. Therefore it was possible that sequence instructions could be operated at the same time during the instruction fetch cycle. In order to reduce the instruction decoding time and the interface time of the data memory interface, an instruction code size was implemented by 16 bits or 32 bits respectively. And the real time debug operation was implemented for easy debugging the designed processor. This FPGA was synthesized by pASIC 2 SpDE and Synplify-Lite synthesis tool of Quick Logic company. The final simulation for worst cases was successfully performed under a Verilog HDL simulation environment. And the FPGA programmed for an 84 pin PLCC package was applied to sequence control system with inputs and outputs of 256 points. The designed processor for the sequence logic was compared with the control system using the DSP(TM320C32-40MHz) and conventional PLC system. The designed processor for the sequence logic showed good performance.

• Proceedings of the Korean Society of Marine Engineers Conference
• /
• 2006.06a
• /
• pp.249-250
• /
• 2006

In this paper, hardware design and implementation of digital controller for the High Precision Digital Power Supply (HPDPS) based on Digital Signal Processor (DSP) and Field Programmable Gate Array (FPGA) is presented. Developed digital controller is composed of high resolution Digital Pulse Width Modulation (DPWM) and high resolution analog to digital converter circuit with anti-aliasing filter. And Digital Signal Processor (DSP) has the capability of a few micro-second calculation time for one feedback loop. 32-bit DSP and DPWM with 150[ps] step resolution is used to implement the HPDPS. Also 18-bit 2 mega sample per second ADC board is adopted for the developed digital controller. Also, hardware structure of the developed digital controller and experimental results of the first prototype board for HPDPS is described.

• Proceedings of the Korean Information Science Society Conference
• /
• 2003.04d
• /
• pp.319-321
• /
• 2003

IMT2000다음으로 개방형 구조를 갖는 차세대 통신 시스템(SDR: Software Defined Radio)에 적용할 수 있는 정보보안 메커니즘으로 블록암호화 알고리즘인 'SEEO'를 구현하였다. SDR의 플랫폼은 주로 프로그래머블(Progammable)한 FPGA가 DSP가 주를 이루는데. 본 논문은 이러한 SDR 시스템 대상으로 적용할 수 있는, 한국형 블록 암호 알고리즘인 'SEED'를 DSP, FPGA로 구현하고 성능비교. 분석을 통하여 효과적이고 합리적인 SDR 암호화 모듈 구현의 방향을 모색해 보았다.

• Journal of Electrical Engineering and Technology
• /
• v.10 no.4
• /
• pp.1655-1666
• /
• 2015

This paper proposes a new approach of Field Programmable Gate Array (FPGA) controlled digital implementation of shunt active power filter (SAPF) under steady state and dynamic operations. Typical implementations of SAPF uses microprocessor and digital signal processor (DSP) but it limited for complex algorithm structure, absence of feedback loop delays and their cost can be exceed the benefit they bring. In this paper, the hardware resources of an FPGA are configured and implemented in order to overcome conventional microcontroller or digital signal processor implementations. This proposed FPGA digital implementation scheme has very less execution time and boosts the overall performance of the system. The FPGA controller integrates the entire control algorithm of an SAPF, including synchronous reference frame transformation, phase locked loop, low pass filter and inverter current controller etc. All these required algorithms are implemented with a single all-on chip FPGA module which provides freedom to reconfigure for any other applications. The entire algorithm is coded, processed and simulated using Xilinx 12.1 ISE suite to estimate the advantages of the proposed system. The coded algorithm is also defused on a single all-on-chip Xilinx Spartan 3A DSP-XC3SD1800 laboratory prototype and experimental results thus obtained match with simulated counterparts under the dynamic state and steady state operating conditions.

• The Journal of the Korea institute of electronic communication sciences
• /
• v.8 no.11
• /
• pp.1707-1712
• /
• 2013

In this paper, we implement a hardware for motor control based on FPGA + embedded processor using Zynq EPP which is All Programmable SoC in order to improve a structural problem of motion control based on such as DSP, MCU and FPGA previously. The implemented motor controller that is fused controller with advantage of FPGA and embedded processor. The signal processing part of high velocity motor control is performed by motor controller based on FPGA. A motion profile and kinematic calculation that are required algorithm process such as operation of a complicate decimal point has processed in an embedded processor based on dual core. As a result of a hardware implementation, it has an advantage that has can be realized an effect of distribution process in one chip. It has also an advantage that is able to organize as a multi-axis motor controller through adding the IP core of motor control implemented on FPGA.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.18 no.9
• /
• pp.2109-2116
• /
• 2014

This paper presents the implementation and design of the advanced WI-FI systems with beam-forming antenna that radiate their power to the direction of user equipment to improve the overall throughput, contrast to the general WI-FI systems equipped with omni-antenna. The system consists of patch array antenna, DSP, FPGA, and Qualcomm's commercial chip. The beam-forming system on the FPGA utilizes the packet information from Qualcomm's commercial chip to control the phase shifters and attenuators of the patch array antenna. The PCI express interface has been used to maximize the communication speed between DSP and FPGA. The directions of arrival of users are managed using the database, and each user is distinguished by the MAC address given from the packet information. When the system wants to transmit a packet to one user, it forms beams to the direction of arrival of the corresponding user stored in the database to maximize the throughput. Directions of arrival of users are estimated using the received preamble in the packet to make its SINR as high as possible. The proposed beam-forming system was implemented using an FPGA and Qualcommm's commercial chip together. The implemented system showed considerable throughput improvement over the existing general AP system with omni-directional antenna in the multi-user communication environment.

• 정보화사회
• /
• s.183
• /
• pp.66-68
• /
• 2006

• Journal of the Korean Institute of Intelligent Systems
• /
• v.20 no.4
• /
• pp.562-568
• /
• 2010

Until now, the implementation of servo motor control units which is being applied in various industrial ares such as industrial system, office equipment, home appliance and robotics, used the MCU and DSC(or DSP). However, MCU and DSC have limitations of not being able to maximize control efficiency of the motor and the flexibility. Thus, in this paper, we propose and implemented the designing method for development of servo motor control IP based on FPGA which have a structure to make the best motor control efficiency and flexibility of control,

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2016.05a
• /
• pp.683-684
• /
• 2016

The up-to-date high-performance DSP or FPGA employs SRIO(Serial Rapid IO) as a high-speed serial communications. SRIO is an industry standard regulated upto Ver 3.1. In this study we developed a backplane having a transmission rate to 15Gbps based on a TI DSP. The back plane icould be used to High-speed video transmission, and will be adopted to connecting multiple DSPs for scalable architecture. This paper will discuss the design constraints for a high-speed communication and multiple-core operation.