• 제어로봇시스템학회:학술대회논문집
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• 2005.06a
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• pp.190-195
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• 2005

The hearing aid chip described in this paper is an analog & digital mixed system. The design focuses on the$\mu$DSP core. This $\mu$DSP core includes internal time delays to two inputs from front and rear microphones. The paper consists of two parts; one is the composure and signal processing algorithm of digital hearing aids and the other is Verilog HDL codes for$\mu$DSP cores. All digital modules in the design were coded and synthesized by Verilog HDL codes which were verified by Mentor Graphics and Synopsis semiconductor chip design tools.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.41 no.2
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• pp.1-8
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• 2004

In this paper, we implement the Digital Signal Processing System based on Human Machine Interface technology for the telematics with embedded noise-robust speech recognition engine and develop the communication system which can be applied to the automobile information center through the human-machine interface technology. Through the embedded speech recognition engine, we can develop the total DSP system based on Human Machine Interface for the telematics in order to test the total system and also the total telematics services.

• Journal of the Institute of Convergence Signal Processing
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• v.10 no.4
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• pp.289-293
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• 2009

This study proposes a novel double-base log encoder (DBLE) for flash Analog-to-Digital converters (ADCs). Analog inputs of flash ADCs are represented in logarithmic number systems with bases of 2 and 3 at the outputs of DBLE. A look up table stores the sets of exponents of base 2 and 3 values. This algorithm improves the performance of a DSP (Digital Signal Processor) system that takes outputs of a flash ADC, since the double-base log number representation does multiplication operation easily within negligible error range in ADC. We have designed and implemented 6 bits DBLE implemented with ROM (Read-Only Memory) architecture in a $0.18\;{\mu}m$ CMOS technology. The power consumption and speed of DBLE are better than the FAT tree and binary ROM encoders at the cost of more chip area. The DBLE can be implemented into SoC architecture with DSP to improve the processing speed.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.2
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• pp.1-13
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• 1999

As the complexity of DSP (Digital Signal Processing) applications increases, the need for new architectures supporting efficient high-level language compilers also grows. By combining several DSP processor specific features, such as single cycle MAC (Multiply-and-ACcumulate), direct memory access, automatic address generation, and hardware looping, with a RISC core having many general purpose registers and orthogonal instructions, a high-performance and compiler-friendly RISC-based DSP processors can be designed. In this study, we develop a code-converter that can exploit these DSP architectural features by post-processing compiler-generated assembly code, and evaluate the performance effects of each feature using seven DSP-kernel benchmarks and a QCELP vocoder program. Finally, we also compare the performances with several existing DSP processors, such as TMS320C3x, TMS320C54x, and TMS320C5x.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.36 no.12C
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• pp.727-737
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• 2011

This paper presents an implementation scheme of real-time lane and vehicle detection system with FPGA and DSP. In this type of implementation, defining the functionality of each device in efficient manner is of crucial importance. The FPGA is in charge of extracting features from input image sequences in reduced form, and the features are provided to the DSP so that tracking lanes and vehicles are performed based on them. In addition, a way of seamless interconnection between those devices is presented. The experimental results show that the system is able to process at least 15 frames per second for video image sequences with size of $640{\times}480$.

• Journal of the Institute of Convergence Signal Processing
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• v.14 no.1
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• pp.62-69
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• 2013

This paper proposes real-time video transmission system by the car-mounted cameras based on MOST Network. Existing vehicles transmit videos by connecting the car-mounted cameras in the form of analog. However, the increase in the number of car-mounted cameras leads to development of the network to connect the cameras. In this paper, DSP is applied to process MPEG 2 encoding/decoding for real-time video transmission in a short period of time. MediaLB is employed to transfer data stream between DSP and MOST network controller. During this procedure, DSP cannot transport data stream directly from MediaLB. Therefore, FPGA is used to deliver data stream transmitting MediaLB to DSP. MediaLB is designed to streamline hardware/software application development for MOST Network and to support all MOST Network data transportation methods. As seen in this paper, the test results verify that real-time video transmission using proposed system operates in a normal matter.

• Journal of Korea Society of Digital Industry and Information Management
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• v.8 no.1
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• pp.117-123
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• 2012

This paper implements mobile Worldwide Interoperability for Microwave Access (WiMAX) receiver using Software Defined Radio (SDR) technology. SDR system is difficult to implement on the mobile handset because of restrictions that are computing power and under space constraints. The implemented receiver processes mobile WiMAX software modem on Open Multimedia Application Platform (OMAP) System on Chip (SoC) and Field Programmable Gate Array (FPGA). OMAP SoC is composed of ARM processor and Digital Signal Processor (DSP). ARM processor supports Single Instruction Multiple Data (SIMD) instruction which could operate on a vector of data with a single instruction and DSP is powerful image and video accelerators. For this reason, we suggest the possibility of SDR technology in the mobile handset. In order to verify the performance of the mobile WiMAX receiver, we measure the software modem runtime respectively. The experimental results show that the proposed receiver is able to do real-time signal processing.

• Proceedings of the Korean Society of Machine Tool Engineers Conference
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• 1995.10a
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• pp.18-23
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• 1995

The study was carried out to develope a precision positioning apparatus, consisting of DC servo motor and piezoelectric actuator. This system is composed of fine and coarse apparatus, measurement system and control system, Piezoelectric actuator is designed for fine positioning. Coarse positioning using lead screw is drived by DC servo motor. Control system output a signal from laser interferometer and microsense to amplifier of DC servo motor and piezoelectric actuator after digital signal processing(DSP). Resolution of this apparatus measure with laser interferometor and microsense

• Proceedings of the Korean Society of Machine Tool Engineers Conference
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• 1999.05a
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• pp.56-62
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• 1999

We make a study of pricisioning apparatus that is used in the various industrial machine. The study was carried out to develope a pricision positioning apparatus, consisting of servo motor and piezoelectric actuator. This system is composed of fine and coarse apparatus, measurement system and control system. Piezoelectric actuator is designed for fine positioning. Coarse positioning using lead screw is drived by servo motor. Control system output a signal from laser interferometer and microsense to amplifier of servo motor and piezoelectric actuator after digital signal processing(DSP). Resolution of this apparatus measure with laser interferometor and microsense so, we can controlled positioning of one output by the coarse positioning in the system. Also we obtain the positioning resolution of 9nm in the system.

• Journal of Broadcast Engineering
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• v.8 no.2
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• pp.116-125
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• 2003

In this paper, we introduce a newly developed DSP module and Software which Is applicable to DTV-OCR and is designed to cancel the interference signal. In general, RF repeater has problems of system oscillation and signal Quality degradation due to feedback interference signal coming from transmit antenna. In this paper, we demonstrate newly developed DSP HW and SW module for cancelling the interference signal by investigating the field data measured through a RF repeater. Also, the structure and signal processing method for non-regenerative repeater system based on the newly developed DSP HW and SW module is illustrated as well.