• Korean Journal of Materials Research
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• v.10 no.9
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• pp.607-611
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• 2000

Zr modified $(Ba_{1-x},Sr_x)TiO_3$ thin films as capacitor for high density DRAM were deposited by r.f. magnetron sputtering. The films deposited at various chamber pressure exhibited a polycrystalline structure. The Zr/Ti ratio of the films increased significantly with decreasing the chamber pressure and this variation affected the microstructure and surface roughness of films When chamber pressure increased dielectric constant of the films effected due to decrease of Zr. The thin films prepared in this study show dielectric constant of 380 to 525 at 100KHz. The variation of capacitance and polarization measured as a function of bias voltage suggested that all films were paraelectric phases. Leakage current exhibited smaller value as chamber pressure decrease and the leakage current density of the films deposited above 10mTorr was $10^{-7}~10^{-8}A/cm^2$ order at 200kV/cm. $(Ba_{1-x},Sr_x)(Ti_{1-y},Zr_y)O_3$ thin films in this study appeared to be potential thin film capacitor for high density DRAM.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.3
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• pp.49-60
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• 2002

A systematic design approach for Power distribution network (PDN) is presented aiming at applications to DRAM module designs. Three main stages are comprised in this design approach: modeling and simulation of a PDN based on a two-dimensional transmission line structure employing a partial element equivalent circuit (PEEC); verification of the simulation results through comparison to measured values; and design space scanning with PDN parameters. Impedance characteristics for do-coupling capacitors are analyzed to devise an effective way to stabilize power and ground plane Performance within a target level of disturbances. Self-impedance and transfer-impedance are studied in terms of distance between circuit features and the size of do-coupling capacitors. A simple equation has been derived to find the do-coupling capacitance values yielding impedance lower than design target, and thereby reducing the overall computation time. The effectiveness of the design methodology has been demonstrated using a DRAM module with discrete do-coupling capacitors and a strip structure.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.19 no.2
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• pp.126-129
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• 2006

We investigated an optimized condition of the capacitor threshold voltage implantation(capacitor $V_T$ Implant) in planar P-MOS DRAM Cell. Several samples with different condition of the capacitor $V_T$ Implant were prepared. It appeared that for the capacitor $V_T$ Implant of $BF_2\;2.0{\times}l0^{13}\;cm^{-2}$ 15 KeV, refresh time is three times larger than that of the sample, in which capacitor $V_T$ Implant is in $BF_2\;1.0{\times}l0^{13}\;cm^{-2}$ 15 KeV. Raphael simulation revealed that the lowed maximum electric field and lowed minimum depletion capacitance ($C_{MIN}$) under the capacitor resulted in well refresh characteristics.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.14 no.1
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• pp.6-11
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• 2001

We studied the feasibility of optical lithography for the critical layers of 0.12${\mu}{\textrm}{m}$ DRAM assuming ArF excimer laser as a light source. To enhance the fidelity of aerial image and process margin, Phase shift mask (PSM) patterns as well as binary mask patterns are corrected with in-house developed Optical Proximity Correction (OPC) software. As the result, w found that the aerial image of critical layers of DRAM cell with 0.12${\mu}{\textrm}{m}$ design rule could not be reproduced with binary masks. But if we use PSM or optical proximity corrected PSM, the fidelity of aerial image ,resolution and process margin are so much enhanced that they could be processed with optical lithography.

• Journal of KIISE:Computer Systems and Theory
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• v.32 no.2
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• pp.85-94
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• 2005

It has been reported and verified in many design experiences that a judicious utilization of the page and burst access modes supported by DRAMs contributes a great reduction in not only the DRAM access latency but also DRAM's energy consumption. Recently, researchers showed that a careful arrangement of data variables in memory directly leads to a maximum utilization of the page and burst access modes for the variable accesses, but unfortunately, found that the problems are not tractable, consequently, resorting to simple (e.g., greedy) heuristic solutions to the problems. In this parer, to improve the quality of existing solutions, we propose 0-1 ILP-based techniques which produce optimal or near-optimal solution depending on the formulation parameters. It is shown that the proposed techniques use on average 32.2%, l5.1% and 3.5% more page accesses, and 84.0%, 113.5% and 10.1% more burst accesses compared to OFU (the order of first use) and the technique in [l, 2] and the technique in [3], respectively.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.11a
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• pp.117-118
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• 2008

High-pressure deuterium annealing process is proposed and investigated for enhanced electrical and reliability properties of 512Mb DDR2 DRAM without increase in process complexity. High pressure deuterium annealing (HPDA) introduced during post metal anneal (PMA) improves not only DRAM performance but also reliability characteristics of MOSFET. Compared with a control sample annealed in a conventional forming gas, additional annealing in a high pressure deuterium ambient at $400^{\circ}C$ for 30 min decreased G1DL current and junction leakage. The improvements can be explained by deuterium incorporation at $SiO_2$/Si substrate interface near isolation trench edge.

• Proceedings of the IEEK Conference
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• 1998.06a
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• pp.530-533
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• 1998

In this paper, a new scheme of a boosted voltage generator (BVG) is designed for low powr DRAM's. The designed BVG can supply stable $V_{pp}$ using a new circuit operting method. This method controls charge pumping capability by switching the supply voltage and ring oscillator frequency of driving circuit, so the BVG can save area and reduce the powr dissipation during $V_{pp}$ maintaining period. The charge pumping circuit of the BVG suffers no $V_{T}$ loss and is to be applicable to low-voltage DRAM's. $V_{pp}$ level detecting circuit can detect constant value of $V_{pp}$ against temperature variation. The level of $V_{pp}$ varies -0.55%~0.098% during its maintaining period. Charge pumping circuit can make $V_{pp}$ level up to 2.95V with $V_{cc}$ =1.5V. The degecting level of $V_{pp}$ level detecting circuit changes -0.34% ~ 0.01% as temperature varies from -20 to 80.deg. C. The powr dissipation during V.$_{pp}$ maintaining period is 4.1mW.W.1mW.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.02a
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• pp.145-145
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• 2010

반도체 소자의 크기가 수십 나노미터 영역으로 줄어들면서, 메모리 소자 또한 미세화를 위해 새로운 기술을 요구하고 있다. 1T DRAM은 하나의 트랜지스터와 하나의 캐패시터 구조를 가진 기존의 DRAM과 달리, 캐패시터 영역을 없애고 하나의 트랜지스터만으로 동작하기 때문에 복잡한 공정과정을 줄일 수 있으며 소자집적화에도 용이하다. 또한 SOI (Silicon-On-Insulator) 기판을 사용함으로써 단채널효과와 누설전류를 감소시키고, 소비전력이 적다는 이점을 가지고 있다. 1T DRAM은 floating body effect에 의해 상부실리콘의 중성영역에 축적된 정공을 이용하여 정보를 저장하게 된다. floating body effect를 발생시키기 위해 본 연구에서는 SOI 기판을 사용한 MOSFET을 사용하였는데, SOI 기판은 불순물 도핑농도에 따라 상부실리콘의 공핍층 두께가 결정된다. 실제로 불순물을 $10^{15}cm^{-3}$ 정도 도핑을 하게 되면 완전공핍된 SOI 구조가 된다. 이는 subthreshold swing값이 작고 저전압, 저전력용 회로에 적합한 특성을 보이기 때문에 부분공핍된 SOI 구조보다 우수한 특성을 가진다. 하지만, 상부실리콘의 중성영역이 완전히 공핍되어 정공이 축적될 공간이 존재하지 않게 된다. 이를 해결하기 위해 기판에 전압을 인가 후 kink effect를 확인하여, 메모리 소자로서의 구동 가능성을 알아보았다. 본 연구에서는 상부실리콘의 두께가 감소함에 따라 1T DRAM의 메모리 특성변화를 관찰하고자, TMAH (Tetramethy Ammonuim Hydroxide) 용액을 이용한 습식식각을 통해 상부실리콘의 두께가 각기 다른 소자를 제작하였다. 제작된 소자는 66 mv/dec의 우수한 subthreshold swing 값을 나타내며 빠른 스위칭 특성을 보였다. 또한 kink effect가 발생하는 최적의 조건을 찾고, 상부실리콘의 두께가 메모리 소자의 쓰기/소거 동작의 경향성에 미치는 영향을 평가하였다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.4
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• pp.1-1
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• 2001

본 논문에서는 μspring 패키지의 구조와 제조공정을 소개하고, 전기적 특성을 μBGA와 비교 분석한 결과를 제시하였다. μBGA에서와 같이 μSpring 패키지의 연결선 인덕턴스 값은 기존의 TSOP 패키지의 반 이하로서 월등한 고속 신호 전달 특성을 제공하게 된다. 또한 μSpring CSP 패키지의 경우 가장 열악한 substrate trace를 가진 핀에서도 2.9nH로 평가되어, Rambus DRAM module의 인덕턴스 규격 상한 값 4nH에 비하여, 약 25% 정도의 margin을 제공한다. μSpring CSP패키지는 μBGA의 약 50%의 제조 비용으로서 μBGA가 만족시키지 못하는 JEDEC Level 1 규격을 충족시킬 뿐만 아니라, thermal cycle 1000회를 통과하는 높은 신뢰성을 제공하여 강력한 경쟁력을 가진다.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.32A no.5
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• pp.737-748
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• 1995

In this paper, we studyed the variables in the design of multichip memory modules with 4M$\times$1bit DRAM chips to construct high capacity and high speed memory modules. The configuration of the module was 8 bit, 16 bit, and 32 bit DRAM modules with employing 0.6 W, 70 nsec 4M$\times$1 bit DRAM chips. We optimized routing area and wiring density by performing the routing experiment with the variables of the chip allocation, module I/O terminal, the number of wiring, and the number of mounting side of the chips. The multichip module was designed to be able to accept MCM-L techiques and low cost PCB materials. The module routing experiment showed that it was an efficient way to align chip I/O terminals and module I/O terminals in parallel when mounting bare chips, and in perpendicular when mounting packaged chips, to set module I/O terminals in two sides, to use double sided substrates, and to allocate chips in a row. The efficient number of wiring layer was 4 layers when designing single sided bare chip mounting modules and 6 layers when constructing double sided bare chip mounting modules whereas the number of wiring layer was 3 layers when using single sided packaged chip mounting substrates and 5 layers when constructing double sided packaged chip mounting substrates. The most efficient configuration was to mount bare chips on doubled substrates and also to increase the number of mounting chips. The fabrication of memory multichip module showed that the modules with bare chips can be reduced to a half in volume and one third in weight comparing to the module with packaged chips. The signal propagation delay time on module substrate was reduced to 0.5-1 nsec.