• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.44 no.2
• /
• pp.19-24
• /
• 2007

With recent advancement of high-speed, multi-gigabit data transmission capabilities, serial links have been more widely adopted in industry than parallel links. Since the parallel link design forces its transmitter to transmit both the data and the clock to the receiver at the same time, it leads to hardware's intricacy during high-speed data transmission, large power consumption, and high cost. Meanwhile, the serial links allows the transmitter to transmit data only with no synchronized clock information. For the purpose, clock and data recovery circuit becomes a very crucial key block. In this paper, a 5.4Gbps half-rate bang-bang CDR is designed for the applications of high-speed graphic DRAM interface. The CDR consists of a half-rate bang-bang phase detector, a current-mirror charge-pump, a 2nd-order loop filter, and a 4-stage differential ring-type VCO. The PD automatically retimes and demultiplexes the data, generating two 2.7Gb/s sequences. The proposed circuit is realized in 66㎚ CMOS process. With input pseudo-random bit sequences (PRBS) of $2^{13}-1$, the post-layout simulations show 10psRMS clock jitter and $40ps_{p-p}$ retimed data jitter characteristics, and also the power dissipation of 80mW from a single 1.8V supply.

• Proceedings of the Korean Vacuum Society Conference
• /
• 2009.02a
• /
• pp.109.1-109.1
• /
• 2009

• Journal of IKEEE
• /
• v.21 no.4
• /
• pp.416-419
• /
• 2017

In this paper, we propose a new digital delay-locked loop (DLL) for high-speed DDR3/DDR4 SDRAMs. The proposed digital DLL adopts a fine delay line using phase interpolation to eliminate the jitter increase problem due to the boundary switching problem. In addition, the proposed digital DLL utilizes a new gradual search algorithm to eliminate the harmonic lock problem. The proposed digital DLL is designed with a 1.1 V, 38-nm CMOS DRAM process and has a frequency operating range of 0.25-2.0 GHz. It has a peak-to-peak jitter of 1.1 ps at 2.0 GHz and has a power consumption of about 13 mW.

• Proceedings of the IEEK Conference
• /
• 2006.06a
• /
• pp.465-466
• /
• 2006

In this paper, novel analog duty cycle corrector (DCC) with a digital duty error detector is proposed. The digital duty error detector measures the duty error of the clock and converts it into a digital code. This digital code is then used to accurately correct the duty ratio by adaptively steering the charge-pump current. The proposed duty cycle corrector was implemented using an 80nm DRAM process with 1.8V supply voltage. The simulation result shows that the proposed duty cycle corrector improves the settling time up to $70{\sim}80%$ at 500MHz clock frequency for the same duty correction accuracy as the conventional analog DCC.

• The Transactions of the Korean Institute of Electrical Engineers C
• /
• v.50 no.4
• /
• pp.176-181
• /
• 2001

As the data rate between chip-to-chip gets high, the skin effect and load of pins deteriorate noise margin. With these, noise disturbances on the bus channel make it difficult for receiver circuits to read the data signal. This paper has proposed a new pre-emphasis driver circuit which achieves wide noise margin by enlarging the signal voltage range during data transition. When data is transferred from a memory chip to a controller, the output boltage of the driver circuit reaches the final values through the intermediate voltage level. The proposed driver supplies more currents applicable to a packet-based memory system, because it needs no additional control signal and realizes very small area. The circuit has been designed in a 0.18 ${\mu}m$ CMOS process, and HSPICE simulation results have shown that the data rate of 1.32 Gbps be achieved. Due to its result, the proposed driver can achieved higher speed than conventional driver by 10%.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2000.11a
• /
• pp.3-5
• /
• 2000

1.8V,4Gb DDR SDRAM설계 및 제작을 수행하였다. DRAM동작 시 발생하는 Bit Line간 CouplingNoise를 보상하기 위한 Twisted Open Bit Line 구조를 제안하였다. Low Voltage Operation으로 인한 Bit Line Sense Amplifier 의 동작 저하를 보상하기 위한 BL S/A Pre-Sensing 방식 및 Reference Bit Line Voltage Calibration 구조를 제안하였다. Chip면적 증가로 인한 동작속도 감소의 보상을 위해 Repeater Driver 구조를 Core 및 Periphery Circuit에 적용하여 동작 대비 Chip 면적의 증가를 최소화 하도록 하였다.

• Asia Marketing Journal
• /
• v.3 no.3
• /
• pp.46-70
• /
• 2001

본 연구는 첨단기술 제품들에서 볼 수 있는 지속적인 기술혁신으로 인하여 새롭게 시장에 진입하는 신규세대 제품과 이전세대 제품들의 동태적 판매량을 묘사하고 예측할 수 있는 모형들을 제시하고 비교·분석하는데 목적이 있다. 본 논문에서는 Bass(1969)의 내구성 소비재에 대한 최초구매 확산모형을 기반으로 하여 개발된 기술적 대체를 반영한 확산모형들, 즉 Norton and Bass(1987), Mahajan and Muller(1996), Jun and Park(1999)의 모형들의 이론적인 틀과 가정들을 비교·분석함으로써 기존 모형과는 변수와 계수의 의미가 다른 모형을 제시하고, 전세계 DRAM 반도체 출하량 자료를 사용하여 모형들 간의 경험적 비교를 행하였다. Jun and Park(1999)이 전세계 DRAM 반도체 출하량 자료에 적용하기 위하여 새롭게 개발한 타입 II 모형(즉 JP2)은 본 연구의 경험적 비교의 결과에 비추어 볼 때 그들의 타입 I 모형이 취한 가정들을 변화시켜서 모형을 구성하는 변수들과 계수들의 의미가 달라진 JPI 모형 또는 Norton and Bass(1987)의 모형(즉 NB1)보다 실제 적용에 있어서 열등할 수 있다는 것을 본 연구는 보여주었다.

• Journal of the Korea Computer Industry Society
• /
• v.6 no.5
• /
• pp.757-766
• /
• 2005

There have been great demands for higher density SRAM in all area of SRAM applications, such as mobile, network, cache, and embedded applications. Therefore, aggressive shrinkage of 6T Full CMOS SRAM had been continued as the technology advances, However, conventional 6T Full CMOS SRAM has a basic limitation in the cell size because it needs 6 transistors on a silicon substrate compared to 1 transistor in a DRAM cell. The typical cell area of 6T Full CMOS SRAM is $70{\sim}90F^{2}$, which is too large compared to $8{\sim}9F^{2}$ of DRAM cell. With 80nm design rule using 193nm ArF lithography, the maximum density is 72M bits at the most. Therefore, pseudo SRAM or 1T SRAM, whose memory cell is the same as DRAM cell, is being adopted for the solution of the high density SRAM applications more than 64M bits. However, the refresh time limits not only the maximum operation temperature but also nearly all critical electrical characteristics of the products such as stand_by current and random access time. In order to overcome both the size penalty of the conventional 6T Full CMOS SRAM cell and the poor characteristics of the TFT load cell, we have developed $S^{3}$ cell. The Load pMOS and the Pass nMOS on ILD have nearly single crystal silicon channel according to the TEM and electron diffraction pattern analysis. In this study, we present $S^{3}$ SRAM cell technology with 100nm design rule in further detail, including the process integration and the basic characteristics of stacked single crystal silicon TFT.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.19 no.4
• /
• pp.314-321
• /
• 2006

There have been great demands for higher density SRAM in all area of SRAM applications, such as mobile, network, cache, and embedded applications. Therefore, aggressive shrinkage of 6 T Full CMOS SRAM had been continued as the technology advances. However, conventional 6 T Full CMOS SRAM has a basic limitation in the cell size because it needs 6 transistors on a silicon substrate compared to 1 transistor in a DRAM cell. The typical cell area of 6 T Full CMOS SRAM is $70{\sim}90\;F^2$, which is too large compared to $8{\sim}9\;F^2$ of DRAM cell. With 80 nm design rule using 193 nm ArF lithography, the maximum density is 72 Mbits at the most. Therefore, pseudo SRAM or 1 T SRAM, whose memory cell is the same as DRAM cell, is being adopted for the solution of the high density SRAM applications more than 64 M bits. However, the refresh time limits not only the maximum operation temperature but also nearly all critical electrical characteristics of the products such as stand_by current and random access time. In order to overcome both the size penalty of the conventional 6 T Full CMOS SRAM cell and the poor characteristics of the TFT load cell, we have developed S3 cell. The Load pMOS and the Pass nMOS on ILD have nearly single crystal silicon channel according to the TEM and electron diffraction pattern analysis. In this study, we present $S^3$ SRAM cell technology with 100 nm design rule in further detail, including the process integration and the basic characteristics of stacked single crystal silicon TFT.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2002.11a
• /
• pp.784-787
• /
• 2002

We prepared the PLT(28) thin film by using sol-gel method and investigated the structure and electrical properties of the film. With the XRD and AFM analyses, it is found that PLT(28) thin film annealed at 6sot has a complete perovskite structure and its surface roughness is about 22$\AA$. We prepared PLT(28) thin film on the Pt/TiO$_{x}$SiO$_2$/Si substrate, in which the specimen has a planar capacitor structure, and analyzed the electrical properties of PLT(28) thin film. In result, PLT(28) thin film has a paraelectric phase and its dielectric constant and loss tangent at 10kHz are 761 and 0.024, respectively. Also, the storage charge density and leakage current density of PLT(28) thin film at W are 134fC/$\mu$m2 and 1.01 $\mu$A/cm2, respectively. As a result of this, we concluded that the PLT(28) thin film is a promising material to be used as a capacitor dielectrics for next generation DRAM.M.