• 산업공학
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• 제25권2호
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• pp.178-186
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• 2012

The DRAM module is an important part of servers, workstations and personal computer. Its malfunction causes a lot of damage on customer system. Therefore, customers demand the highest quality products. The company applies DRAM module Outgoing Quality Assurance Inspection(OQA) to secures the highest quality. It is the key process to decides shipment of products through sample inspection method with customer oriented tests. High fraction of defectives entering to OQA causes inevitable high quality cost. This article proposes the application of ensemble learning to classify the lot status to minimize the ratio of wrong decision in OQA, observing a potential in reducing the wrong decision.

• 전자공학회논문지A
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• 제32A권5호
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• pp.737-748
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• 1995

In this paper, we studyed the variables in the design of multichip memory modules with 4M$\times$1bit DRAM chips to construct high capacity and high speed memory modules. The configuration of the module was 8 bit, 16 bit, and 32 bit DRAM modules with employing 0.6 W, 70 nsec 4M$\times$1 bit DRAM chips. We optimized routing area and wiring density by performing the routing experiment with the variables of the chip allocation, module I/O terminal, the number of wiring, and the number of mounting side of the chips. The multichip module was designed to be able to accept MCM-L techiques and low cost PCB materials. The module routing experiment showed that it was an efficient way to align chip I/O terminals and module I/O terminals in parallel when mounting bare chips, and in perpendicular when mounting packaged chips, to set module I/O terminals in two sides, to use double sided substrates, and to allocate chips in a row. The efficient number of wiring layer was 4 layers when designing single sided bare chip mounting modules and 6 layers when constructing double sided bare chip mounting modules whereas the number of wiring layer was 3 layers when using single sided packaged chip mounting substrates and 5 layers when constructing double sided packaged chip mounting substrates. The most efficient configuration was to mount bare chips on doubled substrates and also to increase the number of mounting chips. The fabrication of memory multichip module showed that the modules with bare chips can be reduced to a half in volume and one third in weight comparing to the module with packaged chips. The signal propagation delay time on module substrate was reduced to 0.5-1 nsec.

• JSTS:Journal of Semiconductor Technology and Science
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• 제1권1호
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• pp.31-39
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• 2001

W polymetal gate technology for giga bit DRAM are presented. Key module processes for polymetal gate are studied in detail. $W/WN_x/poly-silicon$ adopted for a word line of 256Mbit DRAM has good gate oxide integrity and junction leakage characteristics through full integration, which is comparable to those of conventional $WSi_x$/Poly-silicon gate process. These results undoubtedly show that $W/WN_x/poly-silicon$ is the strongest candidate as a word line for Giga bit DRAM.

• 대한전자공학회논문지SD
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• 제39권3호
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• pp.49-60
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• 2002

본 논문에서는 DRAM 모듈의 전원 평면에 대한 효과적인 설계 방법을 제시하였고 그 방법은 다음과 같이 세 단계로 구성되어 있다. 1) PEEC 등가회로를 이용한 2D 전송선 구조로 전원평면의 모델링 및 해석. 2) 측정값 비교를 통한 해석 결과 검증. 3) 전원 평면의 물리적 파라미터를 이용한 설계 가이드 제시. 제시한 내용을 바탕으로 하여 DRAM 모듈에서 전원 및 접지평면 성능을 안정화를 이루기 위한 효과적인 De-coupling 커패시터의 용량과 개수를 결정하는 방법을 기술하였다 이 설계 방법론은 스트립 구조 및 do-coupling 커패시터를 갖는 DRAM 모듈에서 효과적으로 사용할 수 있다.

• 마이크로전자및패키징학회지
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• 제17권4호
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• pp.73-76
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• 2010

A two-facet approach was used to investigate the parametric performance of functional high-speed DDR3 (Double Data Rate) DRAM (Dynamic Random Access Memory) die placed in different types of BGA (Ball Grid Array) packages: wire-bonded BGA (FBGA, Fine Ball Grid Array), flip-chip (FCBGA) and lead-bonded $microBGA^{(R)}$. In the first section, packaged live DDR3 die were tested using automatic test equipment using high-resolution shmoo plots. It was found that the best timing and voltage margin was obtained using the lead-bonded microBGA, followed by the wire-bonded FBGA with the FCBGA exhibiting the worst performance of the three types tested. In particular the flip-chip packaged devices exhibited reduced operating voltage margin. In the second part of this work a test system was designed and constructed to mimic the electrical environment of the data bus in a PC's CPU-Memory subsystem that used a single DIMM (Dual In Line Memory Module) socket in point-to-point and point-to-two-point configurations. The emulation system was used to examine signal integrity for system-level operation at speeds in excess of 6 Gb/pin/sec in order to assess the frequency extensibility of the signal-carrying path of the microBGA considered for future high-speed DRAM packaging. The analyzed signal path was driven from either end of the data bus by a GaAs laser driver capable of operation beyond 10 GHz. Eye diagrams were measured using a high speed sampling oscilloscope with a pulse generator providing a pseudo-random bit sequence stimulus for the laser drivers. The memory controller was emulated using a circuit implemented on a BGA interposer employing the laser driver while the active DRAM was modeled using the same type of laser driver mounted to the DIMM module. A custom silicon loading die was designed and fabricated and placed into the microBGA packages that were attached to an instrumented DIMM module. It was found that 6.6 Gb/sec/pin operation appears feasible in both point to point and point to two point configurations when the input capacitance is limited to 2pF.

• 한국정보통신학회논문지
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• 제8권1호
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• pp.108-114
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• 2004

본 논문은 CF 메모리카드를 이용한 부트 시스템을 제안하고 실제 구현에 관하여 연구한 것이다. 본 논문에서 제안하는 시스템은 고성능의 마이크로프로세서와 적은 양의 프로그램 메모리, CF 메모리카드를 기본으로 구성된다. 여기에 사용자 인터페이스를 위하여 LCD 모듈 및 터치 판넬을 추가된다. 구현된 시스템은 대용량의 Flash 메모리 대신 CF 메모리카드와 DRAM을 이용하여 시스템 단가를 낮출 수 있었으며, 시스템 프로그램이 DRAM에서 실행되기 때문에 시스템 성능이 향상된다.

• 반도체디스플레이기술학회지
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• 제19권3호
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• pp.118-123
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• 2020

In this paper, the design method of asynchronous nonvolatile memory module that can efficiently process and store large amounts of data without loss when the power turned off is proposed and implemented. PSRAM, which takes advantage of DRAM and SRAM, was used for data processing, and NAND flash memory was used for data storage and backup. The problem of a lot of signal interference due to the characteristics of memory devices was solved through PCB design using high-density integration technology. In addition, a boost circuit using the super capacitor of 0.47F was designed to supply sufficient power to the system during the time to back up data when the power is off. As a result, an asynchronous nonvolatile memory module was designed and implemented that guarantees reliability and stability and can semi-permanently store data for about 10 years. The proposed method solved the problem of frequent data loss in industrial sites and presented the possibility of commercialization by providing convenience to users and managers.

• 전자통신동향분석
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• 제35권3호
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• pp.55-65
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• 2020

With the development of nonvolatile memory technology, Intel has released the Optane datacenter persistent memory module (DCPMM) that can be deployed in the dual in-line memory module. The results of research and experiments on Optane DCPMMs are significantly different from the anticipated results in previous studies through emulation. The DCPMM can be used in two different modes, namely, memory mode (similar to volatile DRAM: Dynamic Random Access Memory) and app direct mode (similar to file storage). It has buffers in 256-byte granularity; this is four times the CPU (Central Processing Unit) cache line (i.e., 64 bytes). However, these properties are not easy to use correctly, and the incorrect use of these properties may result in performance degradation. Optane has the same characteristics of DRAM and storage devices. To take advantage of the performance characteristics of this device, operating systems and applications require new approaches. However, this change in computing environments will require a significant number of researches in the future.

• 한국항행학회논문지
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• 제15권6호
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• pp.1104-1110
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• 2011

현재의 반도체 검사장비는 테스트 패턴 프로그램을 위한 메모리로 시스템 설계가 간단하고 리프레시가 필요 없는 SRAM(static random access memory) 모듈을 채용하고 있다. 그러나 SRAM 모듈을 이용한 시스템 구성은 용량이 커질수록 장비의 부피가 증가하기 때문에 메모리 대용량화 및 장비의 소형화에 걸림돌이 되고 있다. DRAM(dynamic random access memory)을 이용하여 반도체 검사 장비를 제작할 경우 SRAM 보다 비용과 장비의 면적이 줄어드는 장점이 있지만 DRAM의 특성 상 메모리 셀 리프레시가 필요하여 정시성을 보장해야 하는 문제가 있다. 따라서 본 논문에서는 이러한 문제를 해결하기 위해 DDR2 SDRAM(double data rate synchronous dynamic random access memory)을 이용한 비메모리 검사장비에서 정시성을 보장해 주는 알고리즘을 제안하고 알고리즘을 이용한 메모리 컨트롤러를 개발하였다. 그 결과, DDR2 SDRAM을 이용할 경우 SRAM을 이용할 때 보다 가격과 면적이 줄어들어 가격측면에서는 13.5배 그리고 면적측면에서는 5.3배 이득이 있음을 확인하였다.

• 대한전자공학회논문지SD
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• 제38권4호
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• pp.1-1
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• 2001

본 논문에서는 μspring 패키지의 구조와 제조공정을 소개하고, 전기적 특성을 μBGA와 비교 분석한 결과를 제시하였다. μBGA에서와 같이 μSpring 패키지의 연결선 인덕턴스 값은 기존의 TSOP 패키지의 반 이하로서 월등한 고속 신호 전달 특성을 제공하게 된다. 또한 μSpring CSP 패키지의 경우 가장 열악한 substrate trace를 가진 핀에서도 2.9nH로 평가되어, Rambus DRAM module의 인덕턴스 규격 상한 값 4nH에 비하여, 약 25% 정도의 margin을 제공한다. μSpring CSP패키지는 μBGA의 약 50%의 제조 비용으로서 μBGA가 만족시키지 못하는 JEDEC Level 1 규격을 충족시킬 뿐만 아니라, thermal cycle 1000회를 통과하는 높은 신뢰성을 제공하여 강력한 경쟁력을 가진다.