• The Journal of the Institute of Internet, Broadcasting and Communication
• /
• v.20 no.1
• /
• pp.193-198
• /
• 2020

The various uses of the Convolutional Neural Network technology are accelerating the evolution of the computing area, but the opposite is causing serious hardware performance shortages. Neural network accelerators, next-generation memory device technologies, and high-bandwidth memory architectures were proposed as countermeasures, but they are difficult to actively introduce due to the problems of versatility, technological maturity, and high cost, respectively. This study proposes DRAM-based main memory technology that enables read operations to be completed without waiting until the end of the refresh operation using pre-stored XOR bit values, even when the refresh operation is performed in the main memory. The results showed that the proposed technique improved performance by 5.8%, saved energy by 1.2%, and improved EDP by 10.6%.

• IEMEK Journal of Embedded Systems and Applications
• /
• v.12 no.4
• /
• pp.193-204
• /
• 2017

Various 3D-stacked DRAMs have been proposed to overcome the memory wall problem. Hybrid Memory Cube (HMC) is a true 3D-stacked DRAM with stacked DRAM layers on top of a logic layer. The logic die is mainly used to implement a memory controller for HMC, and it is connected through a high speed serial link called SerDes with a host that is either a processor or another HMC. In HMC, the serial link is crucial for both performance and power consumption. Therefore, it is important that the link is configured properly so that the required performance should be satisfied while the power consumption is minimized. In this paper, we propose a HMC system model included the high speed serial link to estimate performance accurately. Since the link modeling strictly follows the link flow control mechanism defined in the HMC spec, the actual HMC performance can be estimated accurately with respect to each link configuration. Various simulations are conducted in order to deduce the correlation between the HMC performance and the link configuration with regard to memory utilization. It is confirmed that there is a strong correlation between the achievable maximum performance of HMC and the link configuration in terms of both bandwidth and latency. Therefore, it is possible to find the best link configuration when the required HMC performance is known in advance, and finding the best configuration will lead to significant power saving while the performance requirement is satisfied.

• Journal of IKEEE
• /
• v.20 no.3
• /
• pp.285-290
• /
• 2016

Inter-symbol interference (ISI) due to channel bandwidth limitation constrains the maximum data rate in high speed I/O. Decision feedback equalizer (DFE) is known as the most popular technique for removing ISI. To ensure fast data transmission, not only removing ISI but also raising maximum operating frequency of the circuit itself by relaxing feedback delay margin is important. For single-ended signaling, DFE should cancel out both ISI and high frequency noises. Low-power operation is as important as fast operation because required DFE elements increase as the data rate goes up. This paper surveys recent techniques for fast DFE by removing ISI and high frequency noises, and low power DFE and discusses about their merits and limitations.