• JSTS:Journal of Semiconductor Technology and Science
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• v.12 no.1
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• pp.41-45
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• 2012

We observed that in chemical vapor deposition (CVD) tungsten silicide (WSix) poly gate scheme, the gate oxide thickness decreases as gate length is reduced, and it intensifies the roll-off properties of transistor. This is because the fluorine diffuses laterally from WSix to the gate sidewall oxide in addition to its vertical diffusion to the gate oxide during gate re-oxidation process. When the channel length is very small, the gate oxide thickness is further reduced due to a relative increase of the lateral diffusion than the vertical diffusion. In DRAM cells where the channel length is extremely small, we found the thinned gate oxide is a main cause of poor retention time.

• KIISE Transactions on Computing Practices
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• v.21 no.1
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• pp.88-93
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• 2015

In modern computer systems, DRAM is commonly used as main memory due to its low read/write latency and high endurance. However, DRAM is volatile memory that requires periodic power supply (i.e., memory refresh) to sustain the data stored in it. On the other hand, PCM is a promising candidate for replacement of DRAM because it is non-volatile memory, which could sustain the stored data without memory refresh. PCM is also available for byte-addressable access and in-place update. However, PCM is unsuitable for using main memory of a computer system because it has two limitations: high read/write latency and low endurance. To take the advantage of both DRAM and PCM, a hybrid main memory, which consists of DRAM and PCM, has been suggested and actively studied. In this paper, we propose a novel page replacement algorithm for hybrid main memory. To cope with the weaknesses of PCM, our scheme focuses on reducing the number of PCM writes in the hybrid main memory. Experimental results shows that our proposed page replacement algorithm reduces the number of PCM writes by up to 80.5% compared with the other page replacement algorithms.

• Journal of KIISE
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• v.42 no.11
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• pp.1314-1321
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• 2015

Mobile devices employ buffer cache mechanisms, just as in computer systems such as desktops or servers, to mitigate the performance gap between main memory and secondary storage. However, DRAM has a problem in that it accelerates battery consumption by performing refresh operations periodically to maintain the stored data. In this paper, we propose a novel buffer cache scheme to increase the battery lifecycle in mobile devices based on a hybrid main memory architecture consisting of DRAM and non-volatile PCM. We also suggest a new buffer cache policy that allocates buffers based on process states to optimize the performance and endurance of PCM. In particular, our algorithm allocates each page to the appropriate position corresponding to the state of the application that owns the page, and tries to ensure a rapid response of foreground applications even with a small amount of DRAM memory. The experimental results indicate that the proposed scheme reduces the elapsed time of foreground applications by 58% on average and power consumption by 23% on average without negatively impacting the performance of background applications.

• Journal of Semiconductor Engineering
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• v.1 no.1
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• pp.31-37
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• 2020

We present an approximate DRAM architecture for energy-efficient deep learning. Our key premise is that by bounding memory errors to non-critical information, we can significantly reduce DRAM refresh energy without compromising recognition accuracy of deep neural networks. To validate the key premise, we make extensive Monte-Carlo simulations for several well-known convolutional neural networks such as LeNet, ConvNet and AlexNet with the input of MINIST, CIFAR-10, and ImageNet, respectively. We assume that the highest-order 8-bits (in single precision) and 4-bits (in half precision) are protected from retention errors under the proposed architecture and then, randomly inject bit-errors to unprotected bits with various bit-error-rates. Here, recognition accuracies of the above convolutional neural networks are successfully maintained up to the 10^-5-order bit-error-rate. We simulate DRAM energy during inference of the above convolutional neural networks, where the proposed architecture shows the possibility of considerable energy saving up to 10 ~ 37.5% of total DRAM energy.

• Proceedings of the IEEK Conference
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• 2000.11b
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• pp.325-328
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• 2000

The control of the data retention time is a main issue for realizing future high density dynamic random access memory. In this paper, we propose the new implantation scheme by gate-related ion beam shadowing effect and buffer-enhanced $\Delta$ Rp increase using buffered N- implantation with tilt and 4X-rotation that is designed on the basis of the local-field-enhancement model of the tail component. We report an excellent tail improvement of the retention time distribution attributed to the reduction of electric field across the cell junction due to the redistribution of N- concentration which is intentionally caused by Ion Beam Shadowing and Buffering Effect using tilt implantation with 4X-rotation.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.8
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• pp.54-61
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• 2001

A fully on-chip open-drain CMOS output driver was designed for high bandwidth DRAMs, such that its output voltage swing was insensitive to the variations of temperature and supply voltage. An auto refresh signal was used to update the contents of the current control register, which determined the transistors to be turned-on among the six binary-weighted transistors of an output driver. Because the auto refresh signal is available in DRAM chips, the output driver of this work does not require any external signals to update the current control register. During the time interval while the update is in progress, a negative feedback loop is formed to maintain the low level output voltage ($V_OL$) to be equal to the reference voltage ($V_{OL.ref}$) which is generated by a low-voltage bandgap reference circuit. Test results showed the successful operation at the data rate up to 1Gb/s. The worst-case variations of $V_{OL.ref}$ and $V_OL$ of the proposed output driver were measured to be 2.5% and 7.5% respectively within a temperature range of $20^{\circ}C$ to $90^{\circ}C$ and a supply voltage range of 2.25V to 2.75V, while the worst-case variation of $V_OL$ of the conventional output driver was measured to be 24% at the same temperature and supply voltage ranges.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.17 no.2
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• pp.121-126
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• 2004

In this paper, the effects of the ozone oxidation of the landing polycrystalline silicon on the cell contact resistance of the DRAM device were studied. For this study, the ozone oxidation of the landing polycrystalline silicon layer was performed under various conditions, which was followed by the normal DRAM processes. Then, the cell contact resistance and $t_{WR}$ (write recovery time) of the devices were measured and analyzed. The experimental results showed that the cell contact resistance was more significantly increased for higher temperature of oxidation, longer time of oxidation, and higher concentration of ozone in the oxidation furnace. In addition, the TEM cross-sectional micrographs clearly showed that the oxide layer at the interface between the landing polycrystalline silicon layer and the plug polycrystalline silicon layer was increased by the ozone oxidation. Furthermore, the rate of the device failure due to too large write recovery time was also found to be well correlated with the increase of the cell contact resistance.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.20 no.1
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• pp.193-198
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• 2020

The various uses of the Convolutional Neural Network technology are accelerating the evolution of the computing area, but the opposite is causing serious hardware performance shortages. Neural network accelerators, next-generation memory device technologies, and high-bandwidth memory architectures were proposed as countermeasures, but they are difficult to actively introduce due to the problems of versatility, technological maturity, and high cost, respectively. This study proposes DRAM-based main memory technology that enables read operations to be completed without waiting until the end of the refresh operation using pre-stored XOR bit values, even when the refresh operation is performed in the main memory. The results showed that the proposed technique improved performance by 5.8%, saved energy by 1.2%, and improved EDP by 10.6%.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.4
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• pp.15-24
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• 2000

The dielectric relaxation of high-dielectric capacitors could be understood as a dynamic property of the capacitor in the time domain, which is regarded as a primarily important charge loss mechanism during the refresh time of DRAMs. Therefore, the equivalent circuit of the dielectric relaxation of the high-dielectric capacitor is essentially required to investigate its effects on DRAM. Nevertheless, There is not any theoretical method which is generally applied to realize the equivalent circuit of the dielectric relaxation. Recently, we have developed a novel procedure for the circuit modeling of the dielectric relaxation of high-dielectric capacitor utilizing the frequency domain. This procedure is a general method based on theoretical approach. We have also verified the feasibility of this procedure through experimental process. Finally, we successfully investigated the effect of dielectric relaxation on DRAM operation with the obtained equivalent circuit through this new method.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.21 no.6
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• pp.65-70
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• 2021

Recently, as the number of mobile apps rapidly increases, the memory size of smartphones keeps increasing. Smartphone memory consists of DRAM and as it is a volatile medium, continuous refresh operations for all cells should be performed to maintain the contents. Thus, the power consumption of memory increases in proportion to the DRAM size of the system. There are attempts to configure the memory system with low-power non-volatile memory instead of DRAM to reduce the power consumption of smartphones. However, non-volatile memory has weaknesses in write operations, so analysis of write behaviors is a prerequisite to realize this in practical systems. In this paper, we extract memory reference traces of mobile apps and analyze their characteristics specially focusing on write operations. The results of this paper will be helpful in the design of memory management systems consisting of non-volatile memory in future smartphones.