• 한국인터넷방송통신학회논문지
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• 제20권2호
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• pp.179-185
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• 2020

DRAM은 메인 메모리 시스템을 구성하는 주요한 요소로서 운영체제의 발전, 응용 프로그램의 복잡도와 용량의 증가에 맞추어 DRAM의 용량과 속도 역시 증가하는 추세이다. DRAM은 주기적으로 저장된 값을 읽은 후 다시 저장하는 리프레시 동작을 수행해야 하며, 이에 수반되는 성능 및 파워/에너지 오버헤드는 용량이 증가할수록 더 악화되는 특성을 내재하고 있다. 본 연구는 전하의 보존 시간이 가장 낮은 셀들에 대해서 블룸 필터를 사용하여 64ms, 128ms 이내에 리프레시를 수행해야 하는 로우들을 효율적으로 저장하여 선택적 리프레시를 수행하는 에너지 효율 향상 기법을 제안한다. 실험 결과에 따르면 제안 기법을 통하여 평균 5.5%의 성능 향상이 있었으며, 리프레시 에너지는 평균 76.4% 절감되었고, 평균 EDP는 10.3% 절감된 것으로 나타났다.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1996년도 추계학술대회 논문집 학회본부
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• pp.232-234
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• 1996

The self-refresh mode was introduced as method to reduce power dissipation in DRAM. Because the data retention time of DRAM cell decreases as the ambient temperature rises, the internal period in self-refresh mode must be limited by retention capability at the highest temperature in DRAM specification. Because of this, at room temperature($25^{\circ}C$) unnecessary power dissipation happens, If the period of self-refresh could be modulated as temperature, it is possible to reduce the self-refresh current. In this paper, new temperature detector circuit is suggested as this purpose.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1998년도 하계종합학술대회논문집
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• pp.429-432
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• 1998

The impact of hot carrier induced gate leakage current on the refresh time of memory devices has been examined. The maximum allowable supply voltage for cell transistor has been determined form the degradation of the refresh time. The desing guideline for cell capacitors and refresh circuits has been suggested.

• JSTS:Journal of Semiconductor Technology and Science
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• 제8권1호
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• pp.98-103
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• 2008

1T1C DRAM has been facing technological and physical constraints that make more difficult their further scaling. Thus there are much industrial interests for alternative technologies that exploit new devices and concepts to go beyond the 1T1C DRAM technology, to allow better scaling, and to enlarge the memory performance. The technologies of DRAM cell are changing from 1T1C cell type to capacitor-less 1T-gain cell type for more scalable cell size. But floating body cell (FBC) of 1T-gain DRAM has weak retention properties than 1T1C DRAM. FET-type 1T-FeRAM is not adequate for long term nonvolatile applications, but could be a good alternative for the short term retention applications of DRAM. The proposed nonvolatile refresh scheme is based on utilizing the short nonvolatile retention properties of 1T-FeRAM in both after power-off and power-on operation condition.

• ETRI Journal
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• 제26권6호
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• pp.583-588
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• 2004

In this paper we investigate the effect of a shield metal line inserted between adjacent bit lines on the refresh time and noise margin in a planar DRAM cell. The DRAM cell consists of an access transistor, which is biased to 2.5V during operation, and an NMOS capacitor having the capacitance of 10fF per unit cell and a cell size of $3.63{\mu}m^2$. We designed a 1Mb DRAM with an open bit-line structure. It appears that the refresh time is increased from 4.5 ms to 12 ms when the shield metal line is inserted. Also, it appears that no failure occurs when $V_{cc}$ is increased from 2.2 V to 3 V during a bump up test, while it fails at 2.8 V without a shield metal line. Raphael simulation reveals that the coupling noise between adjacent bit lines is reduced to 1/24 when a shield metal line is inserted, while total capacitance per bit line is increased only by 10%.

• 한국전기전자재료학회논문지
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• 제19권2호
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• pp.126-129
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• 2006

We investigated an optimized condition of the capacitor threshold voltage implantation(capacitor $V_T$ Implant) in planar P-MOS DRAM Cell. Several samples with different condition of the capacitor $V_T$ Implant were prepared. It appeared that for the capacitor $V_T$ Implant of $BF_2\;2.0{\times}l0^{13}\;cm^{-2}$ 15 KeV, refresh time is three times larger than that of the sample, in which capacitor $V_T$ Implant is in $BF_2\;1.0{\times}l0^{13}\;cm^{-2}$ 15 KeV. Raphael simulation revealed that the lowed maximum electric field and lowed minimum depletion capacitance ($C_{MIN}$) under the capacitor resulted in well refresh characteristics.

• JSTS:Journal of Semiconductor Technology and Science
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• 제7권1호
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• pp.1-10
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• 2007

In recent few years, low-power electronics has been a leading drive for technology developments nourished by rapidly growing market share. Mobile DRAM, as a fundamental block of hand-held devices, is now becoming a product developed by limitless competition. To support application specific mobile features, various new power-reduction schemes have been proposed and adopted by standardization. Tightened power budget in battery-operated systems makes conventional schemes not acceptable and increases difficulty of the circuit design. The mobile DRAM has successfully moved down to 1.5V era, and now it is about to move to 1.2V. Further voltage scaling, however, presents critical problems which must be overcome. This paper reviews critical issues in mobile DRAM design and various circuit schemes to solve the problems. Focused on analog circuits, bitline sensing, IO line sensing, refresh-related schemes, DC bias generation, and schemes for higher data rate are covered.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2006년도 하계종합학술대회
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• pp.485-486
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• 2006

This paper proposes a novel low-cost CMOS temperature sensor for controlling the self-refresh period of a mobile DRAM. In this temperature sensor, ring oscillators composed of cascaded inverter stages are used to obtain the temperature of the chip. This method is highly area-efficient, simple and easy for IC implementation as compared to traditional temperature sensors based on analog bandgap reference circuits. The proposed CMOS temperature sensor was fabricated with 80 nm 3-metal DRAM process. It occupies a silicon area of only about less than $0.02\;mm^2$ at $10^{\circ}C$ resolution with under 5uW power consumption at 1 sample/s processing rate. This area is about 33% of conventional temperature sensor in mobile DRAM.

• 한국시뮬레이션학회논문지
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• 제9권4호
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• pp.51-58
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• 2000

The control of the data retention time is a main issue for realizing future high density dynamic random access memory. The novel junction process scheme in sub-micron DRAM cell with STI(Shallow Trench Isolation) has been investigated to improve the tail component in the retention time distribution which is of great importance in DRAM characteristics. In this' paper, we propose the new implantation scheme by gate-related ion beam shadowing effect and buffer-enhanced ${\Delta}Rp$ (projected standard deviation) increase using buffered N-implantation with tilt and 4X(4 times)-rotation that is designed on the basis of the local-field-enhancement model of the tail component. We report an excellent tail improvement of the retention time distribution attributed to the reduction of electric field across the cell junction due to the redistribution of N-concentration which is Intentionally caused by ion Beam Shadowing and Buffering Effect using tilt implantation with 4X-rotation. And also, we suggest the least requirements for adoption of this new implantation scheme and the method to optimize the key parameters such as tilt angle, rotation number, Rp compensation and Nd/Na ratio. We used MEDICI Simulator to confirm the junction device characteristics. And measured the refresh time using the ADVAN Probe tester.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2007년도 하계종합학술대회 논문집
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• pp.433-434
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• 2007

This paper describes a low-voltage dynamic random-access memory (DRAM) focusing on subthreshold leakage reduction during self-refresh (sleep) mode. By sharing a power switch, multiple iterative circuits such as row and column decoders have a significantly reduced subthreshold leakage current. To reduce the leakage current of complex logic gates, dual channel length scheme and input vector control method are used. Because all node voltages during the standby mode are deterministic, zigzag super-cutoff CMOS is used, allowing to Preserve internal data. MTCMOS technique Is also used in the circuits having no need to preserve internal data. Sub-1.2-V 1-Gb mobile DDR DRAM employing all these low-power techniques was designed in a 60 nm CMOS technology and achieved over 77% reduction of overall leakage current during the self-refresh mode.