• 한국시뮬레이션학회논문지
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• 제28권2호
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• pp.15-22
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• 2019

웹 환경 기반 모델링 기술의 발전으로 다양한 산업분야에서 활용할 수 있는 서비스 모델에 대한 시뮬레이션 연구가 진행되고 있다. DEVS 형식론은 시간의 흐름에 따라 다양한 정보를 사용하여 시나리오를 통해 시뮬레이션 할 수 있는 도구로써 활용되고 있다. 또한 DEVS/WS는 웹 기반의 DEVS모델들을 분산컴퓨팅환경을 통해 통합하여, 고성능 컴퓨팅과 데이터 분산 등이 요구되는 시뮬레이션 환경으로 활용이 가능하다. 본 연구에서는 이동 노드 간 공간에 대한 정보를 효율적으로 관리하기 위해 Dynamic Interest Management Model(DIMM)를 제안하여 DEVS/WS 환경에서 시뮬레이션 하였다. DIMM에서 시뮬레이션 중 노드의 효율적인 위치 이동을 위해 Genetic 알고리즘을 통하여 최적의 경로를 유도하게 된다. 본 연구에서는 DIMM의 성능을 평가하기 위해 None Interest Management와 전송메시지 수, 시뮬레이션 시간을 비교하였다. DIMM은 공간정보에 대한 인지도관리를 통해 메시지의 수와 시뮬레이션 시간을 절약하는 성능을 제공하였다.

• 마이크로전자및패키징학회지
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• 제17권4호
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• pp.73-76
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• 2010

A two-facet approach was used to investigate the parametric performance of functional high-speed DDR3 (Double Data Rate) DRAM (Dynamic Random Access Memory) die placed in different types of BGA (Ball Grid Array) packages: wire-bonded BGA (FBGA, Fine Ball Grid Array), flip-chip (FCBGA) and lead-bonded $microBGA^{(R)}$. In the first section, packaged live DDR3 die were tested using automatic test equipment using high-resolution shmoo plots. It was found that the best timing and voltage margin was obtained using the lead-bonded microBGA, followed by the wire-bonded FBGA with the FCBGA exhibiting the worst performance of the three types tested. In particular the flip-chip packaged devices exhibited reduced operating voltage margin. In the second part of this work a test system was designed and constructed to mimic the electrical environment of the data bus in a PC's CPU-Memory subsystem that used a single DIMM (Dual In Line Memory Module) socket in point-to-point and point-to-two-point configurations. The emulation system was used to examine signal integrity for system-level operation at speeds in excess of 6 Gb/pin/sec in order to assess the frequency extensibility of the signal-carrying path of the microBGA considered for future high-speed DRAM packaging. The analyzed signal path was driven from either end of the data bus by a GaAs laser driver capable of operation beyond 10 GHz. Eye diagrams were measured using a high speed sampling oscilloscope with a pulse generator providing a pseudo-random bit sequence stimulus for the laser drivers. The memory controller was emulated using a circuit implemented on a BGA interposer employing the laser driver while the active DRAM was modeled using the same type of laser driver mounted to the DIMM module. A custom silicon loading die was designed and fabricated and placed into the microBGA packages that were attached to an instrumented DIMM module. It was found that 6.6 Gb/sec/pin operation appears feasible in both point to point and point to two point configurations when the input capacitance is limited to 2pF.

• 대한전자공학회논문지SD
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• 제41권10호
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• pp.31-39
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• 2004

이 논문은 파워 잡음 특성이 칩(chip)의 코아 동작에 따라 DDR DRAM용 모듈(Module)과 패키지(package)의 종류의 영향을 받는 다는 것을 보여주고 있다. 이를 분석하기 위해 상용 TSOP-based DIMM 과 FBGA-based DIMM에서 FBGA와 TSOP 패키지형 DRAM 칩을 가지고 임피던스 모양과 파워 잡음을 분석하였다. 일반적인 상식과 달리, FBGA 패키지의 잡음 격리 특성이 TSOP 패키지의 잡음 격리 특성보다 전달되는 잡음에 더 약하고 민감하다는 것이 발견되었다. 또한 자체 및 전달 잡음 특성을 조절하는데 있어서는 모듈상의 디커풀링 커패시터(decoupling capacitors)들 위치가 패키지 자체의 리드선 인덕턴스(lead inductance)보다 더 중요하다는 것을 또한 시뮬레이션 결과들은 보여준다. 따라서 잡음 억제나 잡음 전달로부터 격리의 목표설정 값을 만족시키는 것은 패키지 형태 뿐 아니라 모듈 전체를 고려한 파워 분배 시스템의 설계를 통해서만 얻어질수 있다.

• 한국컴퓨터정보학회:학술대회논문집
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• 한국컴퓨터정보학회 2017년도 제56차 하계학술대회논문집 25권2호
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• pp.275-278
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• 2017

기존의 임베디드 기기의 하드웨어는 리눅스의 장점에도 불구하고 임베디드 기기들의 프로세서나 메모리 등의 하드웨어 자원이 Built-in 형태로 제공되어 시스템 운용 환경 변화에 맞춘 대응이 어렵다. 이러한 문제를 해결하기 위해 본 논문에서는 i.MX6Q SABRE Board for Smart Devices를 참조하여 메모리를 교체할 수 있도록 SO-DIMM을 장착하고 PCIe 이더넷을 추가한 개발보드를 만들었다. 그리고 개발보드에 추가 및 변경 된 하드웨어 디바이스를 활성화한 새로운 임베디드 시스템을 이식하는 방법을 제시한다. 구현 및 성능 분석 결과 새로운 임베디드 시스템에서 운용자는 시스템 운용 시 환경 변화에 대응하여 메모리를 바꾸어 장착할 수 있게 되었고 이로 인해 시스템의 요구사항에 따라 자원의 확정성 및 유연성이 높아짐을 확인하였다.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2007년도 하계종합학술대회 논문집
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• pp.347-348
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• 2007

Most of the power consumption of a LCD TV is form the back light unit. Therefore, technoledge for decreasing the power consumption of the backlight unit is crucial for LCD Tvs. This research suggests a method of decreasing the power comsumption of LCD TV by analyzing the image's RGB info to dimm partitioned backlights independently.

• 천문학논총
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• 제18권1호
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• pp.37-41
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• 2003

We have developed a seeing monitoring system and measured seeing variation of the Bohyunsan Optical Astronomy Observatory (BOAO) and the Sobaeksan Optical Astronomy Observatory (SOAO) using a small telescope system. Our seeing monitoring system is similar to the differential image motion monitor (DIMM) installed at the ESO. The ooly difference between the BOAO and the SOAO seeing monitoring system is a detector system, a video camera at the BOAO and ST-4 camera at the SOAO. We confirmed that the seeing monitoring system at the SOAO can measure average seeing size inspite of its simple detector system. From the BOAO seeing measurement, we found that the seeing size changes fast. We expect that our seeing monitoring system could be used for real time seeing monitoring after some improvement, and the data to be obtained would be very useful when we build adaptive optic system in the future.

• JSTS:Journal of Semiconductor Technology and Science
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• 제8권3호
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• pp.200-209
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• 2008

This paper describes bandwidth linearization techniques in phase-locked loop (PLL) design for common-clock serial link applications. Utilizing a continuously tunable single-input dual-path LC VCO and a constant-gain phase detector, a proposed architecture is well suited to implementing PLLs that must be compliant with standards that specify minimum and maximum allowable bandwidths such as PCI Express Gen2 or FB-DIMM applications. A prototype 4.75 to 6.1-GHz PLL is implemented in 90-nm CMOS. Measurement results show that the PLL bandwidth and random jitter (RJ) variations are well regulated and that the use of a differentially controlled dual-path VCO is important for deterministic jitter (DJ) performance.

• 마이크로전자및패키징학회지
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• 제19권4호
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• pp.45-50
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• 2012

A family of multi-die DRAM packages was developed that incorporate the full functionality of an SODIMM into a single package. Using a common ball assignment analogous to the edge connector of an SODIMM, a broad range of memory types and assembly structures are supported in this new package. In particular DDR3U, LPDDR3 and DDR4RS are all supported. The center-bonded DRAM use face-down wirebond assembly, while the peripherybonded LPDDR3 use the face-up configuration. Flip chip assembly as well as TSV stacked memory is also supported in this new technology. For the center-bonded devices (DDR3, DDR4 and LPDDR3 ${\times}16$ die) and for the face up wirebonded ${\times}32$ LPDDR3 devices, a simple manufacturing flow is used: all die are placed on the strip in a single machine insertion and are sourced from a single wafer. Wirebonding is also a single insertion operation: all die on a strip are wirebonded at the same time. Because the locations of the power signals is unchanged for these different types of memories, a single consolidated set of test hardware can be used for testing and burn-in for all three memory types.

• JSTS:Journal of Semiconductor Technology and Science
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• 제15권5호
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• pp.476-484
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• 2015

Due to the recent advances in non-volatile memory technologies such as PCM, a new memory hierarchy of computer systems is expected to appear. In this paper, we explore the performance of PCM-based swap systems and discuss how this system can be managed efficiently. Specifically, we introduce three management techniques. First, we show that the page fault handling time can be reduced by attaching PCM on DIMM slots, thereby eliminating the software stack overhead of block I/O and the context switch time. Second, we show that it is effective to reduce the page size and turn off the read-ahead option under the PCM swap system where the page fault handling time is sufficiently small. Third, we show that the performance is not degraded even with a small DRAM memory under a PCM swap device; this leads to the reduction of DRAM's energy consumption significantly compared to HDD-based swap systems. We expect that the result of this paper will lead to the transition of the legacy swap system structure of "large memory - slow swap" to a new paradigm of "small memory - fast swap."