• Journal of Institute of Control, Robotics and Systems
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• v.8 no.8
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• pp.706-712
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• 2002

In general, a deadlock in flexible manufacturing systems (FMSs) is caused by a resource limitation and the diversity of routings. However, the deadlock of industrial controllers such as programmable logic controllers (PLCs) can occur from different causes compared with those in general FMSs. The deadlock of PLCs is usually caused by an error signal between PLCs and manufacturing systems. In this paper, we propose a deadlock detection and recovery (DDR) algorithm to resolve the deadlock problem of PLCs at design stage. This paper employs the MAPN (modified automation Petri net), MTPL (modified token passing logic), and ECC (efficient code conversion) algorithm to model manufacturing systems and to convert a Petri net model into a desired LD (ladder diagram). Finally, an example of manufacturing systems is provided to illustrate the proposed DDR algorithm.

• Journal of Advanced Navigation Technology
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• v.15 no.6
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• pp.1104-1110
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• 2011

The conventional semiconductor equipment has adopted SRAM module as the test pattern memory, which has a simple design and does not require refreshing. However, SRAM has its disadvantages as it takes up more space as its capacity becomes larger, making it difficult to meet the requirements of large memories and compact size. if DRAM is adopted as the semiconductor inspection equipment, it takes up less space and costs less than SRAM. However, DRAM is also disadvantageous because it requires the memory cell refresh, which is not suitable for the semiconductor examination equipments that require correct timing. Therefore, In this paper, we will proposed an algorithm for punctuality guarantee of memory-free inspection equipment using DDR2 SDRAM. And we will Developed memory controller using punctuality guarantee algorithm. As the results, show that when we adopt the DDR2 SDRAM, we can get the benefits of saving 13.5 times and 5.3 times in cost and space, respectively, compared to the SRAM.

• Journal of IKEEE
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• v.21 no.4
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• pp.416-419
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• 2017

In this paper, we propose a new digital delay-locked loop (DLL) for high-speed DDR3/DDR4 SDRAMs. The proposed digital DLL adopts a fine delay line using phase interpolation to eliminate the jitter increase problem due to the boundary switching problem. In addition, the proposed digital DLL utilizes a new gradual search algorithm to eliminate the harmonic lock problem. The proposed digital DLL is designed with a 1.1 V, 38-nm CMOS DRAM process and has a frequency operating range of 0.25-2.0 GHz. It has a peak-to-peak jitter of 1.1 ps at 2.0 GHz and has a power consumption of about 13 mW.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2011.05a
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• pp.136-139
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• 2011

The conventional semiconductor equipment has adopted SRAM module as the test pattern memory, which has a simple design and does not require refreshing. However, SRAM has its disadvantages as it takes up more space as its capacity becomes larger, making it difficult to meet the requirements of large memories and compact size. if DRAM is adopted as the semiconductor inspection equipment, it takes up less space and costs less than SRAM. However, DRAM is also disadvantageous because it requires the memory cell refresh, which is not suitable for the semiconductor examination equipments that require correct timing. Therefore, In this paper, we will proposed an algorithm for punctuality guarantee of memory-free inspection equipment using DDR2 SDRAM. And we will produced memory controller using punctuality guarantee algorithm.

• Journal of Korean Institute of Industrial Engineers
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• v.33 no.1
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• pp.153-163
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• 2007

An adaptive framework paradigm where the bandwidth values of the ongoing calls vary according to the trafficsituations is one of the promising concepts for overcoming poor resource conditions due to handoffs in mobilecellular networks. However, quantifying the level of bandwidth degradation of the ongoing calls in an adaptiveframework is important in view of Quality of Service (QoS) Provisioning. Therefore we introduce new QoSparameters, the Degradation Degree Ratio (DDR), which represents the average portion of the degradationdegree during degradation pehod of a call, and the Degradation Area Ratio (DAR), which represents the averageratio of a call's degradation level considering both the period and the degree of degradation jointly in multi-levelbandwidth service. We also develop a new analytical model for estimating the QoS measures such as theDegradation Pehod Ratio (DPR), DDR and DAR. We show how to calculate the QoS measures and illustrate themethod by numerical examples. The proposed model can be used to determine the optimal parameter of theCAC scheme and analyze the sensitivity ofthe QoS parameters in adaptive networks.

• Journal of Korea Multimedia Society
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• v.14 no.3
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• pp.368-377
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• 2011

This paper explains the hardware structure of SURF(Speeded Up Robust Feature) based feature point extractor and its FPGA verification result. SURF algorithm produces novel scale- and rotation-invariant feature point and descriptor which can be used for object recognition, creation of panorama image, 3D Image restoration. But the feature point extraction processing takes approximately 7,200msec for VGA-resolution in embedded environment using ARM11(667Mhz) processor and 128Mbytes DDR memory, hence its real-time operation is not guaranteed. We analyzed integral image memory access pattern which is a key component of SURF algorithm to reduce memory access and memory usage to operate in c real-time. We assure feature extraction that using a Vertex-5 FPGA gives 60frame/sec of VGA image at 100Mhz.

• Journal of information and communication convergence engineering
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• v.13 no.1
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• pp.62-68
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• 2015

In this paper, we propose a watermarking method for protecting the ownership of three-dimensional (3D) content generated from depth and texture images. After selecting the target areas to preserve the watermark by depth-image-based rendering, the reference viewpoint image is moved right and left in the depth map until the maximum viewpoint change is obtained and the overlapped region is generated for marking space. The region is divided into four subparts and scanned. After applying discrete cosine transform, the watermarks are inserted. To extract the watermark, the viewpoint can be changed by referring to the viewpoint image and the corresponding depth image initially, before returning to the original viewpoint. The watermark embedding and extracting algorithm are based on quantization. The watermarked image is attacked by the methods of JPEG compression, blurring, sharpening, and salt-pepper noise.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2014.06a
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• pp.163-165
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• 2014

In this paper, we propose a world's first programmable video processing platform for video quality enhancement of 8K ($7680{\times}4320$) UHD (Ultra High Definition) TV at 60 frames per second. To support huge computation and memory bandwidth of video quality enhancement for 8K resolution, the proposed platform has unique features like symmetric multi-cluster architecture for data partitioning, ring data-path between clusters to support data pipelining, on-the-fly processing architecture to reduce DDR bandwidth, flexible hardware to accelerating common kernel in video enhancement algorithms. In addition to those features, general programmability of SRP (Samsung reconfigurable processor) as main core of the proposed platform makes it possible to upgrade continuously video enhancement algorithm even after the platform is fixed. This ability is very important because algorithms for 8K DTV is under development. The proposed sub-system has been embedded into SoC (System on Chip) and new 8K UHD TV using the programmable SoC is expected at CES2015 for the first time in the world.