• Title/Summary/Keyword: DC.Amplifier

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A 1MHz, 3.3-V Synchornous Buck DC/DC Converter Using CMOS OTAs (CMOS OTA를 이용한 1MHz, 3.3-1 V 동기식 Buck DC/DC 컨버터)

  • Park Kyu-Jin;Kim Hoon;Kim Hee-Jun;Chung Won-Sup
    • Journal of the Institute of Electronics Engineers of Korea SC
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    • v.43 no.5 s.311
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    • pp.28-35
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    • 2006
  • This paper presents a new 3.3-1 V synchronous buck DC/DC converter that employs CMOS operational transconductance amplifiers (OTAs) as circuit-building blocks. An error amplifier OTA in a PWM circuit is compensated for to improve temperature stability. The temperature coefficient of the transconductance gain of the compensated OTA is less than $150\;ppm/^{\circ}C\;over\;0-100^{\circ}C$. The HSPICE simulation results of the $0.3{\mu}m$ standard CMOS technology show that the efficiency of the proposed converter is as high as 80% in the load current range of 40-125 mA. These results show that the proposed converter is adequate for use in battery-operated systems.

Design of a DC-DC Step-Down Converter for LED Backlight of Mobile Devices (휴대기기용 LED 백라이트를 위한 감압형 DC-DC 변환기 설계)

  • Son, Hyun-Sik;Lee, Min-Ji;Park, Won-Kyoung;Song, Han-Jung
    • Journal of the Korea Academia-Industrial cooperation Society
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    • v.15 no.3
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    • pp.1700-1706
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    • 2014
  • In this paper, a step down converter for LED backlight of mobile application has been proposed. The converter which is operated with 4 MHz high switching frequency is capable of reducing mounting area of passive devices consists of a power stage and a control block. Circuit elements of the power stage are inductor, output capacitor, MOS transistors and feedback resistors. The control block consists of pulse width modulator, error amplifier and oscillator etc. Proposed step down converter has been designed and verified using a $0.35{\mu}m$ 1-poly 4-metal BCD process technology. Simulation results show that the output voltage is 1.8 V in 3.7 V input voltage, output current 100 mA which is larger than 25 ~ 50 mA in conventional 500 KHz driven converter when the duty ratio is 0.4.

High Gain and Broadband Millimeter-wave MHEMT Cascode Amplifier (고이득 및 광대역 특성의 밀리미터파 MHEMT Cascode 증폭기)

  • An, Dan;Lee, Bok-Hyung;Lim, Byeong-Ok;Lee, Mun-Kyo;Baek, Yong-Hyun;Chae, Yeon-Sik;Park, Hyung-Moo;Rhee, Jin-Koo
    • Journal of the Institute of Electronics Engineers of Korea TC
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    • v.41 no.8
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    • pp.105-111
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    • 2004
  • In this paper, millimeter-wave high gain and broadband MHEMT cascode amplifiers were designed and fabricated. The 0.1 ${\mu}{\textrm}{m}$ InGaAs/InAlAs/GaAs Metamorphic HEMT was fabricated for cascode amplifiers. The DC characteristics of MHEMT are 640 mA/mm of drain current density, 653 mS/mm of maximum transconductance. The current gain cut-off frequency(f$_{T}$) is 173 GHz and the maximum oscillation frequency(f$_{max}$) is 271 GHz. By using the CPW transmission line, the cascode amplifier was designed the matched circuit for getting the broadband characteristics. The designed amplifier was fabricated by the MHEMT MIMIC process that was developed through this research. As the results of measurement, the 1 stage amplifier obtained 3 dB bandwidth of 37 GHz between 31.3 to 68.3 GHz. Also, this amplifier represents the S21 gain with the average 9.7 dB gain in bandwidth and the maximum gain of 11.3 dB at 40 GHz. The 2 stage amplifier has the broadband characteristics with 3 dB bandwidth of 29.5 GHz in the frequency range from 32.5 to 62.0 GHz. The 2 stage cascode amplifier represents the high gain characteristics with the average gain of 20.4 dB in bandwidth and the maximum gain of 22.3 dB at 36.5 GHz.z.z.

Design and Fabrication of 100 GHz MIMIC Amplifier Using Metamorphic HEMT (Metamorphic HEMT를 이용한 100GHz MIMIC 증폭기의 설계 및 제작)

  • 안단;이복형;임병옥;이문교;백용현;채연식;박형무;이진구
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.41 no.9
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    • pp.25-30
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    • 2004
  • In this Paper, the 0.1 w InGaAs/InAlAs/GaAs Metamorphic HEMT, which is applicable to MIMIC, and a 100 GHz MIMIC amplifier were designed and fabricated. The DC characteristics of MHEMT are 640 mA/mm of drain current density, 653 mS/mm of maximum transconductance. The current gain cut-off frequency(fT) is 173 GHz and the maximum oscillation frequency(fmax) is 271 GHz. A 100 GHz amplifier was designed using 0.1${\mu}{\textrm}{m}$ MHEMT and CPW technology. The measured results from the 100 GHz MIMIC amplifiers show good S21 gain of 10.1 dB and 12.74 dB at 100 GHz and 97.8 GHz, respectively.

A Study on the 8W High Power Amplifier for VSAT at Ku-band (Ku-band의 소형 지구국용을 위한 8W 고출력 증폭기에 관한 연구)

  • 조창환;이찬주;홍의석
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.7 no.1
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    • pp.53-60
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    • 1996
  • The 8W hybrid MIC SSPA has been developed in the frequency range from 14.0 GHz to 14.5 GHz for uplink of KOREASAT's earth station. The whole system was designed of two parts with driving amplifier and high power amplifier to simplify the fabrication process. we reduced weight and volum of power amplifier through arranging the bias circuits in the same housing. The realized SSPA has a small signal gain of $26\pm1dB$within 500 MHz bandwidith, and the input and output return losses are over 7dB and 12dB respectively. The output power of 39.0 ~ 39.2dBm is achieved at the 1dB gain compression point of 14 GHz, 14.25 GHz, and 14.5 GHz. That reveals higher power than 8W of design target. The proposed SSPA manufacture techni- ques in this paper can be applied to the implementation of power amplifiers for some radars and SCPC.

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Design of Ku-Band BiCMOS Low Noise Amplifier (Ku-대역 BiCMOS 저잡음 증폭기 설계)

  • Chang, Dong-Pil;Yom, In-Bok
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.22 no.2
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    • pp.199-207
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    • 2011
  • A Ku-band low noise amplifier has been designed and fabricated by using 0.25 um SiGe BiCMOS process. The developed Ku-band LNA RFIC which has been designed with hetero-junction bipolar transistor(HBT) in the BiCMOS process have noise figure about 2.0 dB and linear gain over 19 dB in the frequency range from 9 GHz to 14 GHz. Optimization technique for p-tap value and electro-magnetic(EM) simulation technique had been used to overcome the inaccuracy in the PDK provided from the foundry service company and to supply the insufficient inductor library. The finally fabricated low noise amplifier of two fabrication runs has been implemented with the size of $0.65\;mm{\times}0.55\;mm$. The pure amplifier circuit layout with the reduced size of $0.4\;mm{\times}0.4\;mm$ without the input and output RF pads and DC bais pads has been incorporated as low noise amplication stages in the multi-function RFIC for the active phased array antenna of Ku-band satellite VSAT.

Realization of a 7.7~8.5GHz 10 W Solid-State Power Amplifier (7.7~8.5 GHz 10 W 반도체 전력 증폭기의 구현에 관한 연구)

  • 박효달;김용구
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.19 no.12
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    • pp.2489-2497
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    • 1994
  • This paper presents the development of a 10 W solid-state hybrid power amplifier(SSPA). operating over $7.7\sim8.5GHz$. The fabrication and measurement of this amplifier are performed with 3 sections, such as the front one for high gain, the middle one for driving, and high power one, to minimize the risk of failure and to increase the easiness of development. and then the final amplifier is realized by connecting 3 sections above mentioned, DC bias circuit, and temperature compensation circuit on one housing. Total small signal gain obtained is about $45\pm1dB$, the input and output return losses are 25 and 27 dB respectively. The output power measured at 1 dB gain compression point for 3 frequencies at 7.7, 8.1, and 8.5 GHz are $39.8\sim40.4dBm$, which is about 10 W. and the 3rd-order harmonic powers of 2 tones test are 13.34 dBc at output power 37.5 dBm. These obtained results satisfies the initially required specification. and the realized SSPA can be installed as a subsystem of the microwave transponder for telecommunication.

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A 6-16 GHz GaN Distributed Power Amplifier MMIC Using Self-bias

  • Park, Hongjong;Lee, Wonho;Jung, Joonho;Choi, Kwangseok;Kim, Jaeduk;Lee, Wangyong;Lee, Changhoon;Kwon, Youngwoo
    • Journal of electromagnetic engineering and science
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    • v.17 no.2
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    • pp.105-107
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    • 2017
  • The self-biasing circuit through a feedback resistor is applied to a gallium nitride (GaN) distributed power amplifier (PA) monolithic microwave circuit (MMIC). The self-biasing circuit is a useful scheme for biasing depletion-mode compound semiconductor devices with a negative gate bias voltage, and is widely used for common source amplifiers. However, the self-biasing circuit is rarely used for PAs, because the large DC power dissipation of the feedback resistor results in the degradation of output power and power efficiency. In this study, the feasibility of applying a self-biasing circuit through a feedback resistor to a GaN PA MMIC is examined by using the high operation voltage of GaN high-electron mobility transistors. The measured results of the proposed GaN PA are the average output power of 41.1 dBm and the average power added efficiency of 12.2% over the 6-16 GHz band.

High Power W-band Power Amplifier using GaN/Si-based 60nm process (GaN/Si 기반 60nm 공정을 이용한 고출력 W대역 전력증폭기)

  • Hwang, Ji-Hye;Kim, Ki-Jin;Kim, Wan-Sik;Han, Jae-Sub;Kim, Min-Gi;Kang, Bong-Mo;Kim, Ki-chul;Choi, Jeung-Won;Park, Ju-man
    • The Journal of the Institute of Internet, Broadcasting and Communication
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    • v.22 no.4
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    • pp.67-72
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    • 2022
  • This study presents the design of power amplifier (PA) in 60 nm GaN/Si HEMT technology. A customized transistor model enables the designing circuits operating at W-band. The all matching network of the PA was composed of equivalent transformer circuit to reduce matching loss. And then, equivalent transformer is several advantages without any additional inductive devices so that a wideband power characteristic can be achieved. The designed die area is 3900 ㎛ × 2300 ㎛. The designed results at center frequency achieved the small signal gain of 15.9 dB, the saturated output power (Psat) of 29.9 dBm, and the power added efficiency (PAE) of 24.2% at the supply voltage of 12 V.

Design of a New Op-Amp for Driving Large-Size LCD Panels (대면적 LCD 패널 구동을 위한 새로운 Op-Amp설계)

  • 이동욱;권오경
    • Proceedings of the IEEK Conference
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    • 2000.06b
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    • pp.133-136
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    • 2000
  • A new Op-Amp output buffer is presented for driving large-size LCD panels. The proposed Op-Amp is designed by combining a common source and a common drain amplifier to have a high slew rate and to minimize the quiescent current. The proposed circuits are simulated in a high-voltage 0.6${\mu}{\textrm}{m}$ CMOS process, dissipates only 20${\mu}{\textrm}{m}$ static current, and have 83dB open-loop DC gain and 60$^{\circ}$phase margin.

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