• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2014.10a
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• pp.267-270
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• 2014

This paper presents a CMOS interface circuit for vibration energy harvesting. The proposed circuit consists of an AC-DC converter and a DC-DC boost converter. The AC-DC converter rectifies the AC signals from vibration devices(PZT), and the DC-DC boost converter generates a boosted and regulated output at a predefined level. A full-wave rectifier using active diodes is used as the AC-DC converter for high efficiency, and a schottky diode type DC-DC boost converter is used for a simple control circuitry. A MPPT(Maximum Power Point Tracking) control is also employed to harvest the maximum power from the PZT. The proposed circuit has been designed in a 0.35um CMOS process. The chip area is $530um{\times}325um$. Simulation results shows that the maximum efficiencies of the AC-DC converter and DC-DC boost converter are 97.7% and 89.2%, respectively. The maximum efficiency of the entire system is 87.2%.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2015.10a
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• pp.412-415
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• 2015

This paper presents a MPPT(Maximum Power Point Tracking) control CMOS interface circuit for vibration energy harvesting. The proposed circuit consists of an AC-DC converter, MPPT Controller, DC-DC boost converter and PMU(Power Management Unit). The AC-DC converter rectifies the AC signals from vibration devices(PZT). MPPT controller is employed to harvest the maximum power from the PZT and increase efficiency of overall system. The DC-DC boost converter generates a boosted and regulated output at a predefined level and provides energy to load using PMU. A full-wave rectifier using active diodes is used as the AC-DC converter for high efficiency, and a schottky diode type DC-DC boost converter is used for a simple control circuitry. The proposed circuit has been designed in a 0.35um CMOS process. The chip area is $950um{\times}920um$.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2011.10a
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• pp.404-407
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• 2011

This paper presents a design of current mode PWM/PFM DC-DC Boost converter. This DC-DC Boost Converter operates with PWM mode at the heavy loads and with PFM mode at light loads. The DC-DC boost converter is designed with CMOS 0.35${\mu}m$ technology. It operates at 500KHz and can drive a load current up to 600mA. It has a maximum power efficiency of 92.1%. The total chip area is $1300{\mu}m{\times}1070{\mu}m$ including pads. The DC-DC boost converter operates in a wide range of load currents while occupying a small chip area.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.8
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• pp.31-40
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• 2009

This paper presents a design of a high performance DC-DC boost converter as a power module for SOC designs. It applied to this chip that reduced inductor and capacitor for integrating on a chip, and it operates with a switching frequency of 100MHz. It has reliability and stability in high switching frequency. The controller of DC-DC boost converter is designed by voltage-mode control method and compensated properly. The designed DC-DC converter is fabricated with the 0.18${\mu}m$ standard CMOS technology with a thick-gate oxide option. The overall die size is 8.14$mm^2$, and controller size is 1.15$mm^2$. The converter has the maximum efficiency over 76% for the output voltage of 4V and load current larger 300mA. The load regulation is 0.012% (0.5mV) for the load current change of 100mA.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.9
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• pp.1755-1762
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• 2016

In this paper, a small areal dual-output SC(switched capacitor) DC-DC converter with a improved range of an input voltage is presented. The conventional SC DC-DC converter has an advantage of low cost and small chip area. But, it has a narrow input voltage range to convert efficiently. Also, it has a lager chip area and a lower power efficiency from multiple outputs. The proposed SC DC-DC converter improves the power efficiency by using the capacitor array structure which efficiently converts the voltage according to the input voltage. By sharing two switch array, it reduces the number of switches and capacitors from 32 to 25. The proposed SC DC-DC converter was manufactured in a $0.18{\mu}m$ CMOS process. In the simulation, the range of the input voltage is 0.7~ 1.8V, the max. power efficiency is 90%, and the chip area is $0.255mm^2$.

• Journal of IKEEE
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• v.16 no.3
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• pp.203-210
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• 2012

Since the non-overlapping gate driver used in conventional DC-DC boost converters generates fixed dead-times, the converters suffer from the body-diode conduction loss or the charge-sharing loss. To reduce the efficiency degradation due to these losses, this paper presents a PWM DC-DC boost converter with adaptive dead-time control. The proposed DC-DC boost converter delivering 3.3V output from a 2.5V input is designed with CMOS $0.3{\mu}m$ technology. It operates at 500kHz and has a maximum power efficiency of 97.3%.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2012.10a
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• pp.285-288
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• 2012

Since the non-overlapping gate driver used in conventional DC-DC boost converters generates fixed dead-times, the converters suffer from the body-diode conduction loss or the charge-sharing loss. To reduce the efficiency degradation due to these losses, this paper presents a PWM DC-DC boost converter with adaptive dead-time control. In light loads, power switching is also employed to increase the efficiency. The designed DC-DC boost converter can thus achieve high efficiency at wide current range. The proposed DC-DC boost converter has 3.3V output from a 2.5V input with 0.18um technology. It operates at 500KHz and has a maximum power efficiency of 97.8%.

• Journal of IKEEE
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• v.15 no.2
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• pp.134-142
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• 2011

This paper describes a tripple-mode high-efficiency DC-DC buck converter. The DC-DC buck converter operate in PWM(Pulse Width Modulation) mode at moderate to heavy loads(100mA~500mA), in PFM(Pulse Frequency Modulation)at light loads(1mA~100mA), and in LDO(Low Drop Out) mode at the sleep mode(<1mA). In PFM mode DPSS(Dynamic Partial Shutdown Strategy) is also employed to increase the efficiency at light loads. The triple-mode converter can thus achieve high efficiencies over wide load current range. The proposed DC-DC converter is designed in a CMOS 0.18um technology. It has a maximum power efficiency of 96.4% and maximum output current of 500mA. The input and output voltages are 3.3V and 2.5V, respectively. The chip size is 1.15mm ${\times}$ 1.10mm including pads.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.22 no.8
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• pp.805-808
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• 2011

This paper presents a design of high-efficiency and high-power class E power transmitter. The transmitter is composed of 300 Watt class E power amplifier and AC-DC converter. The AC-DC converter converts 220 V and 60 Hz AC to a 290 V DC. The generated DC voltage is directly applied to a bias of the class E power amplifier. Because the converter does not have DC-DC converter unit, it has very high conversion efficiency of about 98.03 %. To minimize the loss at the output of the power amplifier, high-Q inductor was implemented and deployed to the output resonant circuit. As a result, the 13.56 MHz class E power amplifier has a high power-added efficiency of 84.2 % at the peak output power of 323.6 W. The overall efficiency of class E power transmitter, including the AC-DC converter, is as high as 82.87 %.

• Journal of IKEEE
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• v.24 no.3
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• pp.853-858
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• 2020

This paper proposes a 2-ch DC-DC converter for OLED display with immunity against RF noise inserted from communication device. For RF signal immunity, an input voltage variation reduction circuit that attenuates as much as the input voltage variation is embedded. The boost converter for positive voltage V_POS operates in SPWM-PWM dual mode and has a dead time controller to increase power efficiency. The inverting charge pump for negative voltage V_NEG is a 2-phase scheme and operates in PFM using VCO to reduce output ripple voltage. Simulation results using 0.18 ㎛ BCDMOS process show that the overshoot and undershoot of the output voltage decrease from 10 mV to 2 mV and 5 mV, respectively. The 2-ch DC-DC converter has power efficiency of 39%~93%, and the power efficiency of the boost converter is up to 3% higher than the conventional method without dead time controller.