• Journal of Power Electronics
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• v.13 no.6
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• pp.1042-1050
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• 2013

This paper presents a study of maximum power point tracking (MPPT) for photovoltaic arrays with only one current sensor. Initially, a review of MPPT methods with only a current sensor is performed with extension for a variety of dc/dc converters. Furthermore, the same topology is developed to achieve better performance in the presence of sensor offset and environmental noise. The proposed method is robust, cost effective, and behaves well dynamically and in the steady state. After a theoretical analysis of presented approach, its validity and effectiveness are verified by simulation and experimental results.

• Proceedings of the KIPE Conference
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• 2014.07a
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• pp.201-202
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• 2014

본 논문에서는 비대칭 하프브리지 컨버터의 비대칭 시비율을 개선한 컨버터를 제안한다. 일반적인 비대칭 하프 브리지 컨버터의 경우 홀드업 타임 조건 때문에 넓은 입력 전압 범위를 가지게 되고, 정상 동작시 스위치의 비대칭 동작이 심화 된다. 이러한 스위치의 비대칭 동작으로 변압기의 자화 전류 옵셋이 증가하고 변압기 부피 및 2차측 정류기들의 전압 불균형이 심화되어 컨버터 효율이 감소하게 된다. 하지만 제안된 컨버터에서는 보조 스위치와 보조 커패시터를 이용, 변압기의 권선비를 조정하여 정상 동작 시 정류기들의 비대칭을 저감하였고, 변압기의 자화 전류 옵셋을 감소시켜 높은 효율을 달성하였다. 제안된 컨버터의 타당성을 검증 하기 위해 300W 프로토 타입을 제작하여 실험을 진행 하였다.

• Journal of Electrical Engineering and Technology
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• v.11 no.4
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• pp.889-897
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• 2016

This paper presents an improved approach for compensating rotor position signal displacement in brushless DC (BLDC) motors with misaligned hall-effect sensors. Typically, the hall-effect sensors in BLDC motors are located in each phase and positioned exactly 120 electrical degrees apart. However, limitations in mechanical tolerances make it difficult to place hall-effect sensors at the correct location. In this paper, a position error compensator to counteract the hall-effect sensor positioning error is proposed. The proposed position error compensator uses least squares error analysis to adjust the relative position error and back-EMF information to reduce the absolute offset error. The effectiveness of the proposed approach is verified through several experiments.

• Journal of electromagnetic engineering and science
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• v.15 no.4
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• pp.232-238
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• 2015

This work describes the development of a D-band (110-170 GHz) signal source based on a SiGe BiCMOS technology. This D-band signal source consists of a V-band (50-75 GHz) oscillator, a V-band amplifier, and a D-band frequency doubler. The V-band signal from the oscillator is amplified for power boost, and then the frequency is doubled for D-band signal generation. The V-band oscillator showed an output power of 2.7 dBm at 67.3 GHz. Including a buffer stage, it had a DC power consumption of 145 mW. The peak gain of the V-band amplifier was 10.9 dB, which was achieved at 64.0 GHz and consumed 110 mW of DC power. The active frequency doubler consumed 60 mW for D-band signal generation. The integrated D-band source exhibited a measured output oscillation frequency of 133.2 GHz with an output power of 3.1 dBm and a phase noise of -107.2 dBc/Hz at 10 MHz offset. The chip size is $900{\times}1,890{\mu}m^2$, including RF and DC pads.

• ETRI Journal
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• v.26 no.3
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• pp.229-240
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• 2004

This paper reports on our development of a dual-mode transceiver for a CMOS high-rate Bluetooth system-onchip solution. The transceiver includes most of the radio building blocks such as an active complex filter, a Gaussian frequency shift keying (GFSK) demodulator, a variable gain amplifier (VGA), a dc offset cancellation circuit, a quadrature local oscillator (LO) generator, and an RF front-end. It is designed for both the normal-rate Bluetooth with an instantaneous bit rate of 1 Mb/s and the high-rate Bluetooth of up to 12 Mb/s. The receiver employs a dualconversion combined with a baseband dual-path architecture for resolving many problems such as flicker noise, dc offset, and power consumption of the dual-mode system. The transceiver requires none of the external image-rejection and intermediate frequency (IF) channel filters by using an LO of 1.6 GHz and the fifth order onchip filters. The chip is fabricated on a $6.5-mm^{2}$ die using a standard $0.25-{\mu}m$ CMOS technology. Experimental results show an in-band image-rejection ratio of 40 dB, an IIP3 of -5 dBm, and a sensitivity of -77 dBm for the Bluetooth mode when the losses from the external components are compensated. It consumes 42 mA in receive ${\pi}/4-diffrential$ quadrature phase-shift keying $({\pi}/4-DQPSK)$ mode of 8 Mb/s, 35 mA in receive GFSK mode of 1 Mb/s, and 32 mA in transmit mode from a 2.5-V supply. These results indicate that the architecture and circuits are adaptable to the implementation of a low-cost, multi-mode, high-speed wireless personal area network.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.9C
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• pp.871-878
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• 2002

The cartesian loop chip which is one of key devices in narrow-band Walky-Talky transmitter using RZ-SSB modulation method was designed and implemented with 0.35 ㎛ CMOS technology. The reduced size and low cost of transmitter were available by the use of direct-conversion and cartesian loop chip, which improved the power efficiency and linearity of transmitter. In addition, low power operation was possible through CMOS technology. The performance test results of transmitter showed -23㏈c improvement of IMD and -30㏈c below suppression of SSB characteristic in the operation of cartesian loop chip (closed-loop). At that time, the transmitting power was about 37㏈m (5W). The main parameters to improve the transmitting characteristic and to compensate the distortion in feed back loop such as DC-offset, loop gain and phase value are interfaced with notebook PC to be controlled with S/W.

• Journal of the Korea Convergence Society
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• v.7 no.3
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• pp.77-85
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• 2016

We propose a digital signal processing technic that can compensate the non-linearity inherent in audio amplifiers, and present the result of the simulation. The inherent non-linearity of the audio power amplifier arising from analog devices is compensated via a digital signal processing technic consisting of indirect learning architecture and an adaptive filter. The simulation results show that the compensator can be realized using a third-order polynomial and compensates odd-order non-linearity efficiently. The even-oder non-linearity is mainly due to the dc offset at the output, which is difficult to eliminate with the proposed method. Care must be taken in designing the bias circuit to avoid the DC offset at the output. The proposed technic has significance in that digital signal processing technic can compensate for the impairment that is an inherent characteristic of an analog system.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.14 no.5
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• pp.472-478
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• 2003

In this paper, a near zero If mixer was designed in cascode structure by using two single-gate FETs. Since it is driven by the second order harmonic of LO signal, a sub-harmonic cascode FET mixer has good LO-RF port isolation characteristic. In order to solve DC offset of a homodyne system, near zero If is used instead of zero If and the mixer is driven by sub-harmonic of LO signal. As RF input power was -30 dBm and LO power was 6 dBm, the designed mixer had 6.7 dB conversion gain, 8.4 dB noise figure, 31.5 dB LO-RF port isolation, -1.9 dBm lIP3 and -2.8 dBm IIP2.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.21 no.5
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• pp.510-518
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• 2010

In this paper, the designed and implemented results of CFL linearization chip which can be used in mobile radio and TRS terminal of UHF band(380~910 MHz), using $0.6\;{\mu}m$ BiCMOS process based on Si, are shown. As gain control circuits for modifying transmit power are inserted not only in feedback path but also in forward path, the stability of CFL is maintained. And, DC-offset correction function of S/H structure, which is suitable for walkie-talkie PTT operation and is easily implemented, is realized. The performance test results of transmitter show that the regulation of FCC emission mask at PEP 3 W(34.8 dBm) is satisfied when the CQPSK modulated signal is fed and more than 30 dBc improvement of 3rd order IMD is achieved when two-tone signal is inputted.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2000.05a
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• pp.205-209
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• 2000

Modem wireless communication equipments provides various multimedia and aims at the development of low-power, minimum size and weight, and low-cost implimentations. Because of the heterodyne architecture which was invented many decades ago in the wireless communication system using too many components, it was difficult to make it small, compact and On-Chip so it does not proper for future communication. That gives rise a new developing architecture, so called, Direct Conversion. Because The Direct Conversion down-converts the wireless frequency band to baseband directly, it does not need using additive components and has a merit of reduction in power dissipation. We describes the Direct Conversion architecture and DC-Offset, which must be solved, theorectically and predicts system performance enhancement when adopt the AC-Coupling method.