• Title/Summary/Keyword: DC Offset

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Compensation Strategy to Eliminate the Effect of Current Measurement Offsets in Grid-Connected Inverters

  • Lee, Chang-Hee;Choi, Jong-Woo
    • Journal of Power Electronics
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    • v.14 no.2
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    • pp.383-391
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    • 2014
  • For the digital control of systems such as grid-connected inverters, measuring inverter output currents accurately is essential. However, current measurement offsets are inevitably generated by current measurement paths and cause DC current components in real inverter output currents. Real inverter output currents with DC components cause the DC-link capacitor voltage to oscillate at the frequency of a utility voltage. For these reasons, current measurement offsets deteriorate the overall system performance. A compensation strategy to eliminate the effect of current measurement offsets in grid-connected inverters is proposed in this study. The validity of the proposed compensation strategy is verified through simulations and experiments. Results show that the proposed compensation strategy improves the performance of grid-connected inverters.

Improved Switching Algorithm for Balancing Neutral Pointed Voltage of Three-Level NPC-Based Dual Active Bridge DC-DC Converter (3-레벨 NPC Dual Active Bridge DC-DC 컨버터의 중성점 전압 제어를 위한 향상된 스위칭 알고리즘)

  • Lee, Jun-Young;Choi, Hyeon-Jun;Cho, Jin-Tae;Jung, Jee-Hoon
    • Proceedings of the KIPE Conference
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    • 2017.07a
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    • pp.235-236
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    • 2017
  • 본 논문에서는 저압 직류 배전 시스템에 사용되는 3-레벨 NPC DAB 컨버터의 중성점 전압 제어를 위한 향상된 스위칭 알고리즘을 제안한다. 3-레벨 NPC DAB 컨버터는 구조상 정격전압 감소를 위해 중성점을 기준으로 DC-link 단에 두 개의 캐패시터가 사용되기 때문에 중성점으로 들어오는 전류에 불균형이 발생하며 중성점 전압이 흔들리는 문제점이 나타난다. 중성점 전압이 흔들릴 경우 불균형한 전압이 변압기에 형성되며 이로 인해 전류 Offset과 실효 전류의 증가에 따른 전력 손실증가 등 전체적인 컨버터의 동작에 악영향을 준다. 따라서 본 논문에서는 3-레벨 NPC DAB 컨버터의 동작원리 및 기존 스위칭 패턴을 분석하고, 향상된 스위칭 패턴을 적용시켜 중성점 전압을 제어하는 알고리즘의 타당성을 모의시험을 통해 검증하고자 한다.

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Frequency Miner Characteristics for Direct Conversion Receiver (직접변환수신기에 적합한 주파수 혼합기의 특성분석)

  • 박필재;유현규;조한진
    • Proceedings of the Korea Electromagnetic Engineering Society Conference
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    • 2000.11a
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    • pp.154-157
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    • 2000
  • One of the problems using DCR(Direct Conversion Receiver) type architecture are DC offset, Poor channel selectivity. APDP(Anti Parallel Diode Pair) can be mood candidate for the DCR frequency mixer due to its inherent 2nd harmonic suppression. APDP shows good IP2 and DC suppression. This paper describes single APDP LO power characteristics, IP2, and receiver structure utilizing APDP frequency mixer.

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Photovoltaic Hot Spot Detection Method Integrated into a Boost Converter (PV Hot Spot 탐지를 위한 부스트 컨버터 설계)

  • Mai, Xuan Hung;Kim, Katherine A.
    • Proceedings of the KIPE Conference
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    • 2015.07a
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    • pp.103-104
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    • 2015
  • Solar energy has proven to be a potential clean energy source to help offset the large consumption of fossil. Nowadays, many research projects aim to enhance photovoltaic (PV) system performance and functionality. This research focuses on integrating self-monitor capability into dc-dc converters that control PV panels to detect a fault in series-connected PV cells, called hot spotting. A detection method using ac parameter characterization is proposed and its operation is examined through simulation.

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Advanced Static Over-modulation Scheme using Offset Voltages Injection for Simple Implementation and Less Harmonics

  • Lee, Dong-Myung
    • Journal of Electrical Engineering and Technology
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    • v.10 no.1
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    • pp.138-145
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    • 2015
  • In this paper, a novel static overmodulation scheme (OVM) for space-vector PWM (SVPWM) is proposed. The proposed static OVM scheme uses the concept of adding offset voltages in linear region as well as overmodulation region to fully utilize DC-link voltage. By employing zero sequence voltage injection, the proposed scheme reduces procedures for achieving SVPWM such as complicated gating time calculation. In addition, this paper proposes a stepwise discontinuous angle movement in high modulation region in order to reduce Total Harmonic Distortion (THD). The validity of the proposed scheme is verified through theoretical analysis and experimental results.

DC Voltage Balancing Control of Half-Bridge PWM Inverter for Liniear Compressor of Refrigerator (냉장고의 선형압축기 구동을 위한 단상 하프브리지 인버터 시스템에서 직류단 불평형 보상에 관한 연구)

  • Kim, Ho-Jin;Kim, Hyeong-Jin;Kim, Dong-Youn;Kim, Jang-Mok
    • The Transactions of the Korean Institute of Power Electronics
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    • v.22 no.3
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    • pp.256-262
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    • 2017
  • This paper presents the control algorithm of a single-phase AC/DC/AC PWM converter for the linear compressor of a refrigerator. The AC/DC/AC converter consists of a full-bridge PWM converter for the control of the input power factor and a half-bridge PWM inverter for the control of the single-phase linear compressor. At the DC-link of this topology, two capacitors are connected in series. These DC-link voltages must be balanced for safe operation. Thus, a new control method of DC voltage balancing for the half-bridge PWM inverter is proposed. The balancing algorithm uses the Integral-Proportional controller and inserts the DC-offset current at the Proportional-Resonant current controller of the inverter to solve the DC-link unbalanced voltages between the two capacitors. The proposed algorithm can be easily implemented without much computation and additional hardware circuit. The usefulness of the proposed algorithm is verified through several experiments.

A 12b 10MS/s CMOS Pipelined ADC Using a Reference Scaling Technique (기준 전압 스케일링을 이용한 12비트 10MS/s CMOS 파이프라인 ADC)

  • Ahn, Gil-Cho
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.46 no.11
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    • pp.16-23
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    • 2009
  • A 12b 10MS/s pipelined ADC with low DC gain amplifiers is presented. The pipelined ADC using a reference scaling technique is proposed to compensate the gain error in MDACs due to a low DC gain amplifier. To minimize the performance degradation of the ADC due to amplifier offset, the proposed offset trimming circuit is employed m the first-stage MDAC amplifier. Additional reset switches are used in all MDACs to reduce the memory effect caused by the low DC gain amplifier. The measured differential and integral non-linearities of the prototype ADC with 45dB DC gain amplifiers are less than 0.7LSB and 3.1LSB, respectively. The prototype ADC is fabricated in a $0.35{\mu}m$ CMOS process and achieves 62dB SNDR and 72dB SFDR with 2.4V supply and 10MHz sampling frequency while consuming 19mW power.

A Fully Integrated Ku-band CMOS VCO with Wide Frequency Tuning (Ku-밴드 광대역 CMOS 전압 제어 발진기)

  • Kim, Young Gi;Hwang, Jae Yeon;Yoon, Jong Deok
    • Journal of the Institute of Electronics and Information Engineers
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    • v.51 no.12
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    • pp.83-89
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    • 2014
  • A ku-band complementary cross-coupled differential voltage controlled oscillator is designed, measured and fabricated using $0.18-{\mu}m$ CMOS technology. A 2.4GHz of very wide frequency tuning at oscillating frequency of 14.5GHz is achieved with presented circuit topology and MOS varactors. Measurement results show -1.66dBm output power with 18mA DC current drive from 3.3V power supply. When 5V is applied, the output power is increased to 0.84dBm with 47mA DC current. -74.5dBc/Hz phase noise at 100kHz offset is measured. The die area is $1.02mm{\times}0.66mm$.

Multi-Channel AD Converters with High-Resolution and Low-Speed (고정밀 저속 다중채널 아날로그-디지털 변환기)

  • Bae, Sung-Hwan;Lee, Chang-Ki
    • The Journal of the Korea institute of electronic communication sciences
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    • v.3 no.3
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    • pp.165-169
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    • 2008
  • Analog-to-Digital converters (ADCs) used in instrumentation and measurements often require high absolute accuracy, including excellent linearity and negligible dc offset. Incremental converters provide a solution for such measurement applications, as they retain most of the advantages of conventional ${\Delta}{\Sigma}$ converters, and yet they are capable of offset-free and accurate conversion. Most of the previous research on incremental converters was for single-channel and dc signal applications, where they can perform extremely accurate data conversion with more than 20-bit resolution. In this paper, a design technique for implementing multiplexed incremental data converters to convert narrow bandwidth ac signals is discussed. A design methodology to optimize the signal-to-quantization+thermal noise ratio of multiplexed IDC is presented. It incorporates the operation principle, topology, and digital decimation filter design. The theoretical results are verified by simulation results.

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A DFT Based Filtering Technique to Eliminate Decaying dc and Harmonics for Power System Phasor Estimation

  • Oh Yong- Taek;Balamourougan V.;Sidhu T.S.
    • KIEE International Transactions on Power Engineering
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    • v.5A no.2
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    • pp.138-143
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    • 2005
  • During faults, the voltage and current signals available to the relay are affected by the decaying dc component and harmonics. In order to make appropriate and accurate decisions, most of the relaying algorithms require the fundamental frequency phasor information that is immune to decaying dc effect and harmonics. The conventional Fourier ph as or estimation algorithm is affected by the presence of decaying-exponential transients in the fault signal. This paper presents a modified Fourier algorithm, which effectively eliminates the decaying dc component and the harmonics present in the fault signal. The decaying dc parameters are estimated by means of an out-of-band filtering technique. The decaying dc offset and harmonics are removed by means of a simple computational procedure that involves the design of two sets of Orthogonal digital OFT filters tuned at different frequencies and by creating three off-line look-up tables. The technique was tested for different decay rates of the decaying dc component. It was also compared with the conventional mimic plus the full cycle OFT algorithm. The results indicate that the proposed technique has a faster convergence to the desired value compared to the conventional mimic plus OFT algorithms over a wide range of decay rates. In all cases, the convergence to the desired value was achieved within one cycle of the power system frequency.